2019-03-05 00:05:42 +01:00
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/*
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* Copyright (c) 2018 naehrwert
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2021-05-12 23:38:34 +02:00
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* Copyright (c) 2019-2020 CTCaer
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2019-03-05 00:05:42 +01:00
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef _MAX7762X_H_
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#define _MAX7762X_H_
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2020-06-26 22:17:06 +02:00
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#include <utils/types.h>
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2019-03-05 00:05:42 +01:00
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/*
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* Switch Power domains (max77620):
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* Name | Usage | uV step | uV min | uV default | uV max | Init
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*-------+---------------+---------+--------+------------+---------+------------------
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2019-09-15 06:16:10 +02:00
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* sd0 | SoC | 12500 | 600000 | 625000 | 1400000 | 1.125V (pkg1.1)
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* sd1 | SDRAM | 12500 | 600000 | 1125000 | 1125000 | 1.1V (pkg1.1)
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* sd2 | ldo{0-1, 7-8} | 12500 | 600000 | 1325000 | 1350000 | 1.325V (pcv)
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* sd3 | 1.8V general | 12500 | 600000 | 1800000 | 1800000 |
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* ldo0 | Display Panel | 25000 | 800000 | 1200000 | 1200000 | 1.2V (pkg1.1)
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* ldo1 | XUSB, PCIE | 25000 | 800000 | 1050000 | 1050000 | 1.05V (pcv)
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* ldo2 | SDMMC1 | 50000 | 800000 | 1800000 | 3300000 |
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2019-09-15 06:16:10 +02:00
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* ldo3 | GC ASIC | 50000 | 800000 | 3100000 | 3100000 | 3.1V (pcv)
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2021-05-12 23:38:34 +02:00
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* ldo4 | RTC | 12500 | 800000 | 850000 | 850000 | 0.85V (AO, pcv)
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2020-04-16 00:18:58 +02:00
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* ldo5 | GC Card | 50000 | 800000 | 1800000 | 1800000 | 1.8V (pcv)
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* ldo6 | Touch, ALS | 50000 | 800000 | 2900000 | 2900000 | 2.9V (pcv)
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* ldo7 | XUSB | 50000 | 800000 | 1050000 | 1050000 | 1.05V (pcv)
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* ldo8 | XUSB, DP, MCU | 50000 | 800000 | 1050000 | 2800000 | 1.05V/2.8V (pcv)
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2019-03-05 00:05:42 +01:00
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*/
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/*
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* MAX77620_AME_GPIO: control GPIO modes (bits 0 - 7 correspond to GPIO0 - GPIO7); 0 -> GPIO, 1 -> alt-mode
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* MAX77620_REG_GPIOx: 0x9 sets output and enable
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*/
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/*! MAX77620 partitions. */
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2021-05-12 23:38:34 +02:00
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#define REGULATOR_SD0 0
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#define REGULATOR_SD1 1
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#define REGULATOR_SD2 2
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#define REGULATOR_SD3 3
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#define REGULATOR_LDO0 4
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#define REGULATOR_LDO1 5
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#define REGULATOR_LDO2 6
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#define REGULATOR_LDO3 7
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#define REGULATOR_LDO4 8
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#define REGULATOR_LDO5 9
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#define REGULATOR_LDO6 10
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#define REGULATOR_LDO7 11
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#define REGULATOR_LDO8 12
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#define REGULATOR_CPU0 13
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#define REGULATOR_GPU0 14
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#define REGULATOR_CPU1 15
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//#define REGULATOR_GPU1 16
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//#define REGULATOR_GPU1 17
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#define REGULATOR_MAX 15
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#define MAX77621_CPU_I2C_ADDR 0x1B
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#define MAX77621_GPU_I2C_ADDR 0x1C
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#define MAX77621_VOUT_REG 0x00
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#define MAX77621_VOUT_DVS_REG 0x01
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#define MAX77621_CONTROL1_REG 0x02
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#define MAX77621_CONTROL2_REG 0x03
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#define MAX77621_CHIPID1_REG 0x04
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#define MAX77621_CHIPID2_REG 0x05
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/* MAX77621_VOUT_DVC_DVS */
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#define MAX77621_DVC_DVS_VOLT_MASK 0x7F
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#define MAX77621_DVC_DVS_ENABLE_SHIFT 7
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#define MAX77621_DVC_DVS_ENABLE_MASK (1 << MAX77621_DVC_DVS_ENABLE_SHIFT)
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/* MAX77621_VOUT */
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#define MAX77621_VOUT_DISABLE 0
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#define MAX77621_VOUT_ENABLE 1
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#define MAX77621_VOUT_ENABLE_MASK (MAX77621_VOUT_ENABLE << MAX77621_DVC_DVS_ENABLE_SHIFT)
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/* MAX77621_CONTROL1 */
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#define MAX77621_RAMP_12mV_PER_US 0x0
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#define MAX77621_RAMP_25mV_PER_US 0x1
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#define MAX77621_RAMP_50mV_PER_US 0x2
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#define MAX77621_RAMP_200mV_PER_US 0x3
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#define MAX77621_RAMP_MASK 0x3
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2020-12-04 19:20:01 +01:00
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#define MAX77621_FREQSHIFT_9PER BIT(2)
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#define MAX77621_BIAS_ENABLE BIT(3)
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#define MAX77621_AD_ENABLE BIT(4)
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#define MAX77621_NFSR_ENABLE BIT(5)
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#define MAX77621_FPWM_EN_M BIT(6)
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#define MAX77621_SNS_ENABLE BIT(7)
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/* MAX77621_CONTROL2 */
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#define MAX77621_INDUCTOR_MIN_30_PER 0
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#define MAX77621_INDUCTOR_NOMINAL 1
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#define MAX77621_INDUCTOR_PLUS_30_PER 2
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#define MAX77621_INDUCTOR_PLUS_60_PER 3
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#define MAX77621_INDUCTOR_MASK 3
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#define MAX77621_CKKADV_TRIP_75mV_PER_US 0x0
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#define MAX77621_CKKADV_TRIP_150mV_PER_US BIT(2)
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#define MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS BIT(3)
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#define MAX77621_CKKADV_TRIP_DISABLE (BIT(2) | BIT(3))
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#define MAX77621_CKKADV_TRIP_MASK (BIT(2) | BIT(3))
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#define MAX77621_FT_ENABLE BIT(4)
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#define MAX77621_DISCH_ENABLE BIT(5)
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#define MAX77621_WDTMR_ENABLE BIT(6)
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#define MAX77621_T_JUNCTION_120 BIT(7)
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#define MAX77621_CPU_CTRL1_POR_DEFAULT (MAX77621_RAMP_50mV_PER_US)
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#define MAX77621_CPU_CTRL1_HOS_DEFAULT (MAX77621_AD_ENABLE | \
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MAX77621_NFSR_ENABLE | \
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MAX77621_SNS_ENABLE | \
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MAX77621_RAMP_12mV_PER_US)
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#define MAX77621_CPU_CTRL2_POR_DEFAULT (MAX77621_T_JUNCTION_120 | \
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MAX77621_FT_ENABLE | \
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MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS | \
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MAX77621_CKKADV_TRIP_150mV_PER_US | \
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MAX77621_INDUCTOR_NOMINAL)
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#define MAX77621_CPU_CTRL2_HOS_DEFAULT (MAX77621_T_JUNCTION_120 | \
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MAX77621_WDTMR_ENABLE | \
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MAX77621_CKKADV_TRIP_75mV_PER_US | \
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MAX77621_INDUCTOR_NOMINAL)
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#define MAX77621_CTRL_HOS_CFG 0
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#define MAX77621_CTRL_POR_CFG 1
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int max77620_regulator_get_status(u32 id);
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int max77620_regulator_config_fps(u32 id);
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int max7762x_regulator_set_voltage(u32 id, u32 mv);
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int max7762x_regulator_enable(u32 id, bool enable);
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void max77620_config_gpio(u32 id, bool enable);
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void max77620_config_default();
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2020-04-16 00:18:58 +02:00
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void max77620_low_battery_monitor_config(bool enable);
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2019-03-05 00:05:42 +01:00
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2021-05-12 23:38:34 +02:00
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void max77621_config_default(u32 id, bool por);
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2019-03-05 00:05:42 +01:00
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#endif
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