add piston nix pkg for iverilog

packages/iverilog/11.0.0/build.sh

@@ -1,17 +0,0 @@
-#!/bin/bash
-
-PREFIX=$(realpath $(dirname $0))
-
-mkdir -p build/iverilog
-cd build/iverilog
-curl -L https://github.com/steveicarus/iverilog/archive/refs/tags/v11_0.tar.gz -o iverilog.tar.gz
-tar xzf iverilog.tar.gz --strip-components=1
-
-chmod +x ./autoconf.sh
-./autoconf.sh
-./configure --prefix="$PREFIX"
-make -j$(nproc)
-make install -j$(nproc)
-
-cd ../../
-rm -rf build

packages/iverilog/11.0.0/compile

@@ -1,4 +0,0 @@
-#!/bin/bash
-
-rename 's/$/\.v/' "$@" # Add .v extension
-iverilog *.v

packages/iverilog/11.0.0/environment

@@ -1,2 +0,0 @@
-#!/bin/bash
-export PATH=$PWD/bin:$PATH

packages/iverilog/11.0.0/metadata.json

@@ -1,5 +0,0 @@
-{
-    "language": "iverilog",
-    "version": "11.0.0",
-    "aliases": ["verilog", "vvp"]
-}

packages/iverilog/11.0.0/run

@@ -1,4 +0,0 @@
-#!/bin/bash
-
-shift
-vvp a.out "$@"

packages/iverilog/11.0.0/test.verilog

@@ -1,7 +0,0 @@
-module hello;
-  initial
-    begin
-      $display("OK");
-      $finish ;
-    end
-endmodule

runtimes/default.nix

@@ -41,4 +41,5 @@ args: {
     "julia" = import ./julia.nix args;
     "jelly" = import ./jelly.nix args;
     "openjdk-java" = import ./openjdk-java.nix args;
+    "iverilog" = import ./iverilog.nix args;
 }

runtimes/iverilog.nix

@@ -0,0 +1,43 @@
+{pkgs, piston, ...}:
+let
+    pkg = pkgs.verilog;
+in piston.mkRuntime {
+    language = "iverilog";
+    version = pkg.version;
+
+    aliases = [
+        "verilog"
+        "vvp"
+    ];
+
+    compile = ''
+        rename 's/$/\.v/' "$@" # Add .v extension
+        ${pkg}/bin/iverilog *.v
+    '';
+
+    run = ''
+        shift
+        ${pkg}/bin/vvp a.out "$@"
+    '';
+
+    tests = [
+        (piston.mkTest {
+            files = {
+                "test.verilog" = ''
+                    module ok;
+                        initial
+                            begin
+                            $display("OK");
+                            $finish ;
+                            end
+                    endmodule
+
+                '';
+            };
+            args = [];
+            stdin = "";
+            packages = [];
+            main = "test.verilog";
+        })
+    ];
+}