487 lines
16 KiB
C
487 lines
16 KiB
C
/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2021 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include <soc/hw_init.h>
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#include <display/di.h>
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#include <input/joycon.h>
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#include <input/touch.h>
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#include <sec/se.h>
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#include <sec/se_t210.h>
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#include <soc/bpmp.h>
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#include <soc/clock.h>
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#include <soc/fuse.h>
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#include <soc/gpio.h>
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#include <soc/i2c.h>
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#include <soc/pinmux.h>
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#include <soc/pmc.h>
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#include <soc/uart.h>
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#include <soc/t210.h>
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#include <mem/mc.h>
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#include <mem/minerva.h>
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#include <mem/sdram.h>
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#include <power/bq24193.h>
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#include <power/max77620.h>
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#include <power/max7762x.h>
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#include <power/regulator_5v.h>
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#include <storage/nx_sd.h>
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#include <storage/sdmmc.h>
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#include <thermal/fan.h>
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#include <thermal/tmp451.h>
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#include <utils/util.h>
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extern boot_cfg_t b_cfg;
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extern volatile nyx_storage_t *nyx_str;
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/*
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* CLK_OSC - 38.4 MHz crystal.
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* CLK_M - 19.2 MHz (osc/2).
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* CLK_S - 32.768 KHz (from PMIC).
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* SCLK - 204MHz init (-> 408MHz -> OC).
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* HCLK - 204MHz init (-> 408MHz -> OC).
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* PCLK - 68MHz init (-> 136MHz -> OC/4).
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*/
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u32 hw_get_chip_id()
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{
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if (((APB_MISC(APB_MISC_GP_HIDREV) >> 4) & 0xF) >= GP_HIDREV_MAJOR_T210B01)
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return GP_HIDREV_MAJOR_T210B01;
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else
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return GP_HIDREV_MAJOR_T210;
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}
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static void _config_oscillators()
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{
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CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 4; // Set CLK_M_DIVISOR to 2.
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SYSCTR0(SYSCTR0_CNTFID0) = 19200000; // Set counter frequency.
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TMR(TIMERUS_USEC_CFG) = 0x45F; // For 19.2MHz clk_m.
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CLOCK(CLK_RST_CONTROLLER_OSC_CTRL) = 0x50000071; // Set OSC to 38.4MHz and drive strength.
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PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFFFFF81) | 0xE; // Set LP0 OSC drive strength.
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PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFBFFFFF) | PMC_OSC_EDPD_OVER_OSC_CTRL_OVER;
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PMC(APBDEV_PMC_CNTRL2) = (PMC(APBDEV_PMC_CNTRL2) & 0xFFFFEFFF) | PMC_CNTRL2_HOLD_CKE_LOW_EN;
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PMC(APBDEV_PMC_SCRATCH188) = (PMC(APBDEV_PMC_SCRATCH188) & 0xFCFFFFFF) | (4 << 23); // LP0 EMC2TMC_CFG_XM2COMP_PU_VREF_SEL_RANGE.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 0x10; // Set HCLK div to 2 and PCLK div to 1.
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CLOCK(CLK_RST_CONTROLLER_PLLMB_BASE) &= 0xBFFFFFFF; // PLLMB disable.
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PMC(APBDEV_PMC_TSC_MULT) = (PMC(APBDEV_PMC_TSC_MULT) & 0xFFFF0000) | 0x249F; //0x249F = 19200000 * (16 / 32.768 kHz)
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SYS) = 0; // Set BPMP/SCLK div to 1.
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CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444; // Set BPMP/SCLK source to Run and PLLP_OUT2 (204MHz).
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CLOCK(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER) = 0x80000000; // Enable SUPER_SDIV to 1.
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CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3.
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}
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// The uart is skipped for Copper, Hoag and Calcio. Used in Icosa, Iowa and Aula.
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static void _config_gpios(bool nx_hoag)
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{
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// Clamp inputs when tristated.
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APB_MISC(APB_MISC_PP_PINMUX_GLOBAL) = 0;
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if (!nx_hoag)
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{
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PINMUX_AUX(PINMUX_AUX_UART2_TX) = 0;
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PINMUX_AUX(PINMUX_AUX_UART3_TX) = 0;
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// Set pin mode for UARTB/C TX pins.
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#if !defined (DEBUG_UART_PORT) || DEBUG_UART_PORT != UART_B
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gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_GPIO);
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#endif
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#if !defined (DEBUG_UART_PORT) || DEBUG_UART_PORT != UART_C
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gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_GPIO);
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#endif
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// Enable input logic for UARTB/C TX pins.
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gpio_output_enable(GPIO_PORT_G, GPIO_PIN_0, GPIO_OUTPUT_DISABLE);
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gpio_output_enable(GPIO_PORT_D, GPIO_PIN_1, GPIO_OUTPUT_DISABLE);
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}
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// Set Joy-Con IsAttached direction.
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PINMUX_AUX(PINMUX_AUX_GPIO_PE6) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE;
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PINMUX_AUX(PINMUX_AUX_GPIO_PH6) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE;
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// Set Joy-Con IsAttached mode.
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gpio_config(GPIO_PORT_E, GPIO_PIN_6, GPIO_MODE_GPIO);
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gpio_config(GPIO_PORT_H, GPIO_PIN_6, GPIO_MODE_GPIO);
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// Enable input logic for Joy-Con IsAttached pins.
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gpio_output_enable(GPIO_PORT_E, GPIO_PIN_6, GPIO_OUTPUT_DISABLE);
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gpio_output_enable(GPIO_PORT_H, GPIO_PIN_6, GPIO_OUTPUT_DISABLE);
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pinmux_config_i2c(I2C_1);
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pinmux_config_i2c(I2C_5);
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pinmux_config_uart(UART_A);
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// Configure volume up/down as inputs.
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gpio_config(GPIO_PORT_X, GPIO_PIN_6, GPIO_MODE_GPIO);
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gpio_config(GPIO_PORT_X, GPIO_PIN_7, GPIO_MODE_GPIO);
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gpio_output_enable(GPIO_PORT_X, GPIO_PIN_6, GPIO_OUTPUT_DISABLE);
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gpio_output_enable(GPIO_PORT_X, GPIO_PIN_7, GPIO_OUTPUT_DISABLE);
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// Configure HOME as inputs.
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// PINMUX_AUX(PINMUX_AUX_BUTTON_HOME) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE;
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// gpio_config(GPIO_PORT_Y, GPIO_PIN_1, GPIO_MODE_GPIO);
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}
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static void _config_pmc_scratch()
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{
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PMC(APBDEV_PMC_SCRATCH20) &= 0xFFF3FFFF; // Unset Debug console from Customer Option.
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PMC(APBDEV_PMC_SCRATCH190) &= 0xFFFFFFFE; // Unset DATA_DQ_E_IVREF EMC_PMACRO_DATA_PAD_TX_CTRL
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PMC(APBDEV_PMC_SECURE_SCRATCH21) |= PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT;
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}
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static void _mbist_workaround()
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{
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// Make sure Audio clocks are enabled before accessing I2S.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= BIT(CLK_V_AHUB);
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= BIT(CLK_Y_APE);
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// Set mux output to SOR1 clock switch.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) | 0x8000) & 0xFFFFBFFF;
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// Enabled PLLD and set csi to PLLD for test pattern generation.
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CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) |= 0x40800000;
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// Clear per-clock resets for APE/VIC/HOST1X/DISP1.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_CLR) = BIT(CLK_Y_APE);
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_CLR) = BIT(CLK_X_VIC);
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1);
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usleep(2);
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// I2S channels to master and disable SLCG.
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I2S(I2S1_CTRL) |= I2S_CTRL_MASTER_EN;
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I2S(I2S1_CG) &= ~I2S_CG_SLCG_ENABLE;
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I2S(I2S2_CTRL) |= I2S_CTRL_MASTER_EN;
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I2S(I2S2_CG) &= ~I2S_CG_SLCG_ENABLE;
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I2S(I2S3_CTRL) |= I2S_CTRL_MASTER_EN;
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I2S(I2S3_CG) &= ~I2S_CG_SLCG_ENABLE;
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I2S(I2S4_CTRL) |= I2S_CTRL_MASTER_EN;
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I2S(I2S4_CG) &= ~I2S_CG_SLCG_ENABLE;
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I2S(I2S5_CTRL) |= I2S_CTRL_MASTER_EN;
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I2S(I2S5_CG) &= ~I2S_CG_SLCG_ENABLE;
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DISPLAY_A(_DIREG(DC_COM_DSC_TOP_CTL)) |= 4; // DSC_SLCG_OVERRIDE.
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VIC(0x8C) = 0xFFFFFFFF;
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usleep(2);
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// Set per-clock reset for APE/VIC/HOST1X/DISP1.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_SET) = BIT(CLK_Y_APE);
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1);
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_SET) = BIT(CLK_X_VIC);
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// Enable specific clocks and disable all others.
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// CLK L Devices.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) =
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BIT(CLK_H_PMC) |
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BIT(CLK_H_FUSE);
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// CLK H Devices.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) =
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BIT(CLK_L_RTC) |
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BIT(CLK_L_TMR) |
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BIT(CLK_L_GPIO) |
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BIT(CLK_L_BPMP_CACHE_CTRL);
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// CLK U Devices.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_U) =
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BIT(CLK_U_CSITE) |
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BIT(CLK_U_IRAMA) |
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BIT(CLK_U_IRAMB) |
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BIT(CLK_U_IRAMC) |
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BIT(CLK_U_IRAMD) |
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BIT(CLK_U_BPMP_CACHE_RAM);
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// CLK V Devices.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) =
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BIT(CLK_V_MSELECT) |
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BIT(CLK_V_APB2APE) |
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BIT(CLK_V_SPDIF_DOUBLER) |
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BIT(CLK_V_SE);
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// CLK W Devices.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_W) =
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BIT(CLK_W_PCIERX0) |
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BIT(CLK_W_PCIERX1) |
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BIT(CLK_W_PCIERX2) |
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BIT(CLK_W_PCIERX3) |
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BIT(CLK_W_PCIERX4) |
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BIT(CLK_W_PCIERX5) |
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BIT(CLK_W_ENTROPY) |
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BIT(CLK_W_MC1);
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// CLK X Devices.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_X) =
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BIT(CLK_X_MC_CAPA) |
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BIT(CLK_X_MC_CBPA) |
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BIT(CLK_X_MC_CPU) |
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BIT(CLK_X_MC_BBC) |
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BIT(CLK_X_GPU) |
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BIT(CLK_X_DBGAPB) |
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BIT(CLK_X_PLLG_REF);
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// CLK Y Devices.
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CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) =
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BIT(CLK_Y_MC_CDPA) |
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BIT(CLK_Y_MC_CCPA);
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// Disable clock gate overrides.
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA) = 0;
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB) = 0;
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC) = 0;
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) = 0;
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CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE) = 0;
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// Set child clock sources.
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CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) &= 0x1F7FFFFF; // Disable PLLD and set reference clock and csi clock.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) &= 0xFFFF3FFF; // Set SOR1 to automatic muxing of safe clock (24MHz) or SOR1 clk switch.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT.
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}
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static void _config_se_brom()
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{
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// Enable fuse clock.
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clock_enable_fuse(true);
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// Skip SBK/SSK if running on patched Erista.
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if (!(FUSE(FUSE_PRIVATE_KEY0) == 0xFFFFFFFF))
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{
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// Bootrom part we skipped.
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u32 sbk[4] = {
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FUSE(FUSE_PRIVATE_KEY0),
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FUSE(FUSE_PRIVATE_KEY1),
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FUSE(FUSE_PRIVATE_KEY2),
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FUSE(FUSE_PRIVATE_KEY3)
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};
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// Set SBK to slot 14.
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se_aes_key_set(14, sbk, SE_KEY_128_SIZE);
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// Lock SBK from being read.
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se_key_acc_ctrl(14, SE_KEY_TBL_DIS_KEYREAD_FLAG);
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// Lock SSK (although it's not set and unused anyways).
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se_key_acc_ctrl(15, SE_KEY_TBL_DIS_KEYREAD_FLAG);
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}
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// This memset needs to happen here, else TZRAM will behave weirdly later on.
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memset((void *)TZRAM_BASE, 0, 0x10000);
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PMC(APBDEV_PMC_CRYPTO_OP) = PMC_CRYPTO_OP_SE_ENABLE;
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SE(SE_INT_STATUS_REG) = 0x1F; // Clear all SE interrupts.
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// Clear the boot reason to avoid problems later
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PMC(APBDEV_PMC_SCRATCH200) = 0x0;
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PMC(APBDEV_PMC_RST_STATUS) = 0x0;
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APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) = (APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) & 0xF0) | (7 << 10);
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}
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static void _config_regulators(bool tegra_t210)
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{
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// Set RTC/AO domain to POR voltage.
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if (tegra_t210)
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max7762x_regulator_set_voltage(REGULATOR_LDO4, 1000000);
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// Disable low battery shutdown monitor.
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max77620_low_battery_monitor_config(false);
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// Disable SDMMC1 IO power.
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gpio_write(GPIO_PORT_E, GPIO_PIN_4, GPIO_LOW);
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max7762x_regulator_enable(REGULATOR_LDO2, false);
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sd_power_cycle_time_start = get_tmr_ms();
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CNFGBBC, MAX77620_CNFGBBC_RESISTOR_1K);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1,
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MAX77620_ONOFFCNFG1_RSVD | (3 << MAX77620_ONOFFCNFG1_MRT_SHIFT)); // PWR delay for forced shutdown off.
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if (tegra_t210)
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{
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// Configure all Flexible Power Sequencers for MAX77620.
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG0, (7 << MAX77620_FPS_TIME_PERIOD_SHIFT));
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG1, (7 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (1 << MAX77620_FPS_EN_SRC_SHIFT));
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG2, (7 << MAX77620_FPS_TIME_PERIOD_SHIFT));
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max77620_regulator_config_fps(REGULATOR_LDO4);
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max77620_regulator_config_fps(REGULATOR_LDO8);
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max77620_regulator_config_fps(REGULATOR_SD0);
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max77620_regulator_config_fps(REGULATOR_SD1);
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max77620_regulator_config_fps(REGULATOR_SD3);
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_GPIO3,
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(4 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (2 << MAX77620_FPS_PD_PERIOD_SHIFT)); // 3.x+
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// Set vdd_core voltage to 1.125V.
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max7762x_regulator_set_voltage(REGULATOR_SD0, 1125000);
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// Fix CPU/GPU after L4T warmboot.
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max77620_config_gpio(5, MAX77620_GPIO_OUTPUT_DISABLE);
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max77620_config_gpio(6, MAX77620_GPIO_OUTPUT_DISABLE);
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// Set POR configuration.
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max77621_config_default(REGULATOR_CPU0, MAX77621_CTRL_POR_CFG);
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max77621_config_default(REGULATOR_GPU0, MAX77621_CTRL_POR_CFG);
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}
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else // Tegra X1+ set vdd_core voltage to 1.05V.
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max7762x_regulator_set_voltage(REGULATOR_SD0, 1050000);
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}
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void hw_init()
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{
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// Get Chip ID.
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bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210;
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bool nx_hoag = fuse_read_hw_type() == FUSE_NX_HW_TYPE_HOAG;
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// Bootrom stuff we skipped by going through rcm.
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_config_se_brom();
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//FUSE(FUSE_PRIVATEKEYDISABLE) = 0x11;
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SYSREG(AHB_AHB_SPARE_REG) &= 0xFFFFFF9F; // Unset APB2JTAG_OVERRIDE_EN and OBS_OVERRIDE_EN.
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PMC(APBDEV_PMC_SCRATCH49) = PMC(APBDEV_PMC_SCRATCH49) & 0xFFFFFFFC;
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// Perform Memory Built-In Self Test WAR if T210.
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if (tegra_t210)
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_mbist_workaround();
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// Enable Security Engine clock.
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clock_enable_se();
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// Enable Fuse clock.
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clock_enable_fuse(true);
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|
// Disable Fuse programming.
|
|
fuse_disable_program();
|
|
|
|
// Enable clocks to Memory controllers and disable AHB redirect.
|
|
mc_enable();
|
|
|
|
// Initialize counters, CLKM, BPMP and other clocks based on 38.4MHz oscillator.
|
|
_config_oscillators();
|
|
|
|
// Initialize pin configuration.
|
|
_config_gpios(nx_hoag);
|
|
|
|
#ifdef DEBUG_UART_PORT
|
|
clock_enable_uart(DEBUG_UART_PORT);
|
|
uart_init(DEBUG_UART_PORT, DEBUG_UART_BAUDRATE);
|
|
uart_invert(DEBUG_UART_PORT, DEBUG_UART_INVERT, UART_INVERT_TXD);
|
|
#endif
|
|
|
|
// Enable Dynamic Voltage and Frequency Scaling device clock.
|
|
clock_enable_cl_dvfs();
|
|
|
|
// Enable clocks to I2C1 and I2CPWR.
|
|
clock_enable_i2c(I2C_1);
|
|
clock_enable_i2c(I2C_5);
|
|
|
|
// Enable clock to TZRAM.
|
|
clock_enable_tzram();
|
|
|
|
// Initialize I2C5, mandatory for PMIC.
|
|
i2c_init(I2C_5);
|
|
|
|
//! TODO: Why? Device is NFC MCU on Lite.
|
|
if (nx_hoag)
|
|
{
|
|
max7762x_regulator_set_voltage(REGULATOR_LDO8, 2800000);
|
|
max7762x_regulator_enable(REGULATOR_LDO8, true);
|
|
}
|
|
|
|
// Initialize I2C1 for various power related devices.
|
|
i2c_init(I2C_1);
|
|
|
|
// Initialize various regulators based on Erista/Mariko platform.
|
|
_config_regulators(tegra_t210);
|
|
|
|
// Enable charger in case it's disabled.
|
|
bq24193_enable_charger();
|
|
|
|
_config_pmc_scratch(); // Missing from 4.x+
|
|
|
|
// Set BPMP/SCLK to PLLP_OUT (408MHz).
|
|
CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333;
|
|
|
|
// Disable TZRAM shutdown control and lock the regs.
|
|
if (!tegra_t210)
|
|
{
|
|
PMC(APBDEV_PMC_TZRAM_PWR_CNTRL) &= 0xFFFFFFFE;
|
|
PMC(APBDEV_PMC_TZRAM_NON_SEC_DISABLE) = 3;
|
|
PMC(APBDEV_PMC_TZRAM_SEC_DISABLE) = 3;
|
|
}
|
|
|
|
// Initialize External memory controller and configure DRAM parameters.
|
|
sdram_init();
|
|
|
|
bpmp_mmu_enable();
|
|
}
|
|
|
|
void hw_reinit_workaround(bool coreboot, u32 bl_magic)
|
|
{
|
|
// Disable BPMP max clock.
|
|
bpmp_clk_rate_set(BPMP_CLK_NORMAL);
|
|
|
|
#ifdef NYX
|
|
// Disable temperature sensor, touchscreen, 5V regulators and Joy-Con.
|
|
tmp451_end();
|
|
set_fan_duty(0);
|
|
touch_power_off();
|
|
jc_deinit();
|
|
regulator_5v_disable(REGULATOR_5V_ALL);
|
|
#endif
|
|
|
|
// Flush/disable MMU cache and set DRAM clock to 204MHz.
|
|
bpmp_mmu_disable();
|
|
minerva_change_freq(FREQ_204);
|
|
nyx_str->mtc_cfg.init_done = 0;
|
|
|
|
// Re-enable clocks to Audio Processing Engine as a workaround to hanging.
|
|
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= BIT(CLK_V_AHUB);
|
|
CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= BIT(CLK_Y_APE);
|
|
|
|
// Do coreboot mitigations.
|
|
if (coreboot)
|
|
{
|
|
msleep(10);
|
|
|
|
clock_disable_cl_dvfs();
|
|
|
|
// Disable Joy-con GPIOs.
|
|
gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO);
|
|
gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO);
|
|
gpio_config(GPIO_PORT_E, GPIO_PIN_6, GPIO_MODE_SPIO);
|
|
gpio_config(GPIO_PORT_H, GPIO_PIN_6, GPIO_MODE_SPIO);
|
|
|
|
// Reinstate SD controller power.
|
|
PMC(APBDEV_PMC_NO_IOPOWER) &= ~(PMC_NO_IOPOWER_SDMMC1_IO_EN);
|
|
}
|
|
|
|
// Seamless display or display power off.
|
|
switch (bl_magic)
|
|
{
|
|
case BL_MAGIC_CRBOOT_SLD:;
|
|
// Set pwm to 0%, switch to gpio mode and restore pwm duty.
|
|
u32 brightness = display_get_backlight_brightness();
|
|
display_backlight_brightness(0, 1000);
|
|
gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_GPIO);
|
|
display_backlight_brightness(brightness, 0);
|
|
break;
|
|
default:
|
|
display_end();
|
|
}
|
|
|
|
// Enable clock to USBD and init SDMMC1 to avoid hangs with bad hw inits.
|
|
if (bl_magic == BL_MAGIC_BROKEN_HWI)
|
|
{
|
|
CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_USBD);
|
|
sdmmc_init(&sd_sdmmc, SDMMC_1, SDMMC_POWER_3_3, SDMMC_BUS_WIDTH_1, SDHCI_TIMING_SD_ID, 0);
|
|
clock_disable_cl_dvfs();
|
|
|
|
msleep(200);
|
|
}
|
|
}
|