Merge hekate 5.1.0 changes
This commit is contained in:
shchmue
parent
cdb29719e4
commit
b3a739592e
46 changed files with 1525 additions and 224 deletions
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@ -19,6 +19,7 @@
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#include "bpmp.h"
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#include "clock.h"
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#include "t210.h"
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#include "../../common/memory_map.h"
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#include "../utils/util.h"
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#define BPMP_CACHE_CONFIG 0x0
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@ -74,13 +75,13 @@
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bpmp_mmu_entry_t mmu_entries[] =
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{
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{ 0x80000000, 0xFFFFFFFF, MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC | MMU_EN_CACHED, true },
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{ IPL_LOAD_ADDR, 0x40040000, MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC | MMU_EN_CACHED, true }
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{ DRAM_START, 0xFFFFFFFF, MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC | MMU_EN_CACHED, true },
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{ IRAM_BASE, 0x4003FFFF, MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC | MMU_EN_CACHED, true }
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};
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void bpmp_mmu_maintenance(u32 op)
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void bpmp_mmu_maintenance(u32 op, bool force)
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{
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if (!(BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) & CFG_ENABLE))
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if (!force && !(BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) & CFG_ENABLE))
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return;
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BPMP_CACHE_CTRL(BPMP_CACHE_INT_CLEAR) = INT_CLR_MAINT_DONE;
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@ -132,13 +133,13 @@ void bpmp_mmu_enable()
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BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_COPY_SHADOW;
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// Invalidate cache.
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY);
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY, true);
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// Enable cache.
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BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) = CFG_ENABLE | CFG_FORCE_WRITE_THROUGH | CFG_TAG_CHK_ABRT_ON_ERR;
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// HW bug. Invalidate cache again.
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY);
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY, false);
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}
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void bpmp_mmu_disable()
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@ -147,21 +148,19 @@ void bpmp_mmu_disable()
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return;
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// Clean and invalidate cache.
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY);
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false);
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// Disable cache.
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BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) = 0;
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// HW bug. Invalidate cache again.
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY);
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}
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const u8 pllc4_divn[] = {
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0, // BPMP_CLK_NORMAL: 408MHz 0% - 136MHz APB.
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85, // BPMP_CLK_LOW_BOOST: 544MHz 33% - 136MHz APB.
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90, // BPMP_CLK_MID_BOOST: 576MHz 41% - 144MHz APB.
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94 // BPMP_CLK_SUPER_BOOST: 602MHz 48% - 150MHz APB.
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//95 // BPMP_CLK_SUPER_BOOST: 608MHz 49% - 152MHz APB.
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85, // BPMP_CLK_HIGH_BOOST: 544MHz 33% - 136MHz APB.
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90, // BPMP_CLK_SUPER_BOOST: 576MHz 41% - 144MHz APB.
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92 // BPMP_CLK_HYPER_BOOST: 589MHz 44% - 147MHz APB.
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// Do not use for public releases!
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//95 // BPMP_CLK_DEV_BOOST: 608MHz 49% - 152MHz APB.
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};
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bpmp_freq_t bpmp_clock_set = BPMP_CLK_NORMAL;
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@ -36,13 +36,16 @@ typedef struct _bpmp_mmu_entry_t
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typedef enum
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{
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BPMP_CLK_NORMAL, // 408MHz 0% - 136MHz APB.
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BPMP_CLK_LOW_BOOST, // 544MHz 33% - 136MHz APB.
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BPMP_CLK_MID_BOOST, // 576MHz 41% - 144MHz APB.
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BPMP_CLK_SUPER_BOOST, // 608MHz 49% - 152MHz APB.
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BPMP_CLK_HIGH_BOOST, // 544MHz 33% - 136MHz APB.
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BPMP_CLK_SUPER_BOOST, // 576MHz 41% - 144MHz APB.
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BPMP_CLK_HYPER_BOOST, // 589MHz 44% - 147MHz APB.
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//BPMP_CLK_DEV_BOOST, // 608MHz 49% - 152MHz APB.
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BPMP_CLK_MAX
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} bpmp_freq_t;
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void bpmp_mmu_maintenance(u32 op);
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#define BPMP_CLK_DEFAULT_BOOST BPMP_CLK_HYPER_BOOST
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void bpmp_mmu_maintenance(u32 op, bool force);
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void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply);
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void bpmp_mmu_enable();
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void bpmp_mmu_disable();
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@ -15,7 +15,6 @@
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*/
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#include "../soc/clock.h"
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#include "../soc/kfuse.h"
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#include "../soc/t210.h"
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#include "../utils/util.h"
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#include "../storage/sdmmc.h"
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@ -30,13 +29,14 @@ static const clock_t _clock_uart[] = {
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/* UART E */ { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE, 20, 0, 2 }
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};
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//I2C default parameters - TLOW: 4, THIGH: 2, DEBOUNCE: 0 FM_DIV: 26.
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static const clock_t _clock_i2c[] = {
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/* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 12, 6, 0 }, // 0, 19 }, // 100KHz
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/* I2C2 */ { 0 },
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/* I2C3 */ { 0 },
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/* I2C4 */ { 0 },
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/* I2C5 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 15, 6, 0 }, // 0, 4 }, // 400KHz
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/* I2C6 */ { 0 }
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/* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 12, 0, 19 }, //20.4MHz -> 100KHz
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/* I2C2 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C2, 22, 0, 4 }, //81.6MHz -> 400KHz
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/* I2C3 */ { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_I2C3, 3, 0, 4 }, //81.6MHz -> 400KHz
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/* I2C4 */ { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_I2C4, 7, 0, 19 }, //20.4MHz -> 100KHz
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/* I2C5 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 15, 0, 4 }, //81.6MHz -> 400KHz
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/* I2C6 */ { CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_I2C6, 6, 0, 19 } //20.4MHz -> 100KHz
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};
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static clock_t _clock_se = {
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@ -74,7 +74,7 @@ static clock_t _clock_coresight = {
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};
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static clock_t _clock_pwm = {
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CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, 17, 6, 4 // Freference: 6.2MHz.
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CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, 17, 6, 4 // Fref: 6.2MHz.
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};
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void clock_enable(const clock_t *clk)
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@ -88,6 +88,8 @@ void clock_enable(const clock_t *clk)
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CLOCK(clk->source) = clk->clk_div | (clk->clk_src << 29);
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// Enable.
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CLOCK(clk->enable) = (CLOCK(clk->enable) & ~(1 << clk->index)) | (1 << clk->index);
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usleep(2);
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// Take clock off reset.
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CLOCK(clk->reset) &= ~(1 << clk->index);
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}
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@ -189,7 +191,6 @@ void clock_enable_kfuse()
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usleep(10);
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CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) &= 0xFFFFFEFF;
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usleep(20);
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kfuse_wait_ready();
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}
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void clock_disable_kfuse()
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@ -368,7 +369,7 @@ static void _clock_sdmmc_clear_enable(u32 id)
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static u32 _clock_sdmmc_table[8] = { 0 };
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#define PLLP_OUT0 0x0
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static int _clock_sdmmc_config_clock_source_inner(u32 *pout, u32 id, u32 val)
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static int _clock_sdmmc_config_clock_host(u32 *pout, u32 id, u32 val)
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{
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u32 divisor = 0;
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u32 source = PLLP_OUT0;
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@ -416,6 +417,7 @@ static int _clock_sdmmc_config_clock_source_inner(u32 *pout, u32 id, u32 val)
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_clock_sdmmc_table[2 * id] = val;
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_clock_sdmmc_table[2 * id + 1] = *pout;
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// Set SDMMC clock.
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switch (id)
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{
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case SDMMC_1:
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@ -446,15 +448,16 @@ void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val)
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int is_enabled = _clock_sdmmc_is_enabled(id);
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if (is_enabled)
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_clock_sdmmc_clear_enable(id);
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_clock_sdmmc_config_clock_source_inner(pout, id, val);
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_clock_sdmmc_config_clock_host(pout, id, val);
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if (is_enabled)
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_clock_sdmmc_set_enable(id);
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_clock_sdmmc_is_reset(id);
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}
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}
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void clock_sdmmc_get_params(u32 *pout, u16 *pdivisor, u32 type)
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void clock_sdmmc_get_card_clock_div(u32 *pout, u16 *pdivisor, u32 type)
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{
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// Get Card clock divisor.
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switch (type)
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{
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case 0:
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@ -515,7 +518,7 @@ void clock_sdmmc_enable(u32 id, u32 val)
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if (_clock_sdmmc_is_enabled(id))
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_clock_sdmmc_clear_enable(id);
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_clock_sdmmc_set_reset(id);
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_clock_sdmmc_config_clock_source_inner(&div, id, val);
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_clock_sdmmc_config_clock_host(&div, id, val);
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_clock_sdmmc_set_enable(id);
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_clock_sdmmc_is_reset(id);
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usleep((100000 + div - 1) / div);
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@ -104,6 +104,7 @@
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SYS 0x400
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410
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#define CLK_RST_CONTROLLER_CLK_SOURCE_SE 0x42C
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#define CLK_RST_CONTROLLER_RST_DEV_V_CLR 0x434
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#define CLK_RST_CONTROLLER_CLK_ENB_V_SET 0x440
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#define CLK_RST_CONTROLLER_CLK_ENB_V_CLR 0x444
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#define CLK_RST_CONTROLLER_CLK_ENB_W_SET 0x448
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@ -181,7 +182,7 @@ void clock_disable_coresight();
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void clock_enable_pwm();
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void clock_disable_pwm();
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void clock_sdmmc_config_clock_source(u32 *pout, u32 id, u32 val);
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void clock_sdmmc_get_params(u32 *pout, u16 *pdivisor, u32 type);
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void clock_sdmmc_get_card_clock_div(u32 *pout, u16 *pdivisor, u32 type);
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int clock_sdmmc_is_not_reset_and_enabled(u32 id);
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void clock_sdmmc_enable(u32 id, u32 val);
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void clock_sdmmc_disable(u32 id);
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@ -80,9 +80,9 @@ void cluster_boot_cpu0(u32 entry)
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_cluster_enable_power();
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if (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x40000000))
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if (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x40000000)) // PLLX_ENABLE.
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{
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CLOCK(CLK_RST_CONTROLLER_PLLX_MISC_3) &= 0xFFFFFFF7;
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CLOCK(CLK_RST_CONTROLLER_PLLX_MISC_3) &= 0xFFFFFFF7; // Disable IDDQ.
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usleep(2);
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CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x80404E02;
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CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x404E02;
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@ -127,6 +127,9 @@ void cluster_boot_cpu0(u32 entry)
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SB(SB_CSR) = SB_CSR_NS_RST_VEC_WR_DIS;
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(void)SB(SB_CSR);
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// Tighten up the security aperture.
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// MC(MC_TZ_SECURITY_CTRL) = 1;
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// Clear MSELECT reset.
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CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_V) &= 0xFFFFFFF7;
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// Clear NONCPU reset.
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@ -22,6 +22,34 @@
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#include "../soc/fuse.h"
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#include "../soc/t210.h"
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#define ARRAYSIZE(x) (sizeof(x) / sizeof(*x))
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static const u32 evp_thunk_template[] = {
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0xe92d0007, // STMFD SP!, {R0-R2}
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0xe1a0200e, // MOV R2, LR
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0xe2422002, // SUB R2, R2, #2
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0xe5922000, // LDR R2, [R2]
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0xe20220ff, // AND R2, R2, #0xFF
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0xe1a02082, // MOV R2, R2,LSL#1
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0xe59f001c, // LDR R0, =evp_thunk_template
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0xe59f101c, // LDR R1, =thunk_end
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0xe0411000, // SUB R1, R1, R0
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0xe59f0018, // LDR R0, =iram_evp_thunks
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0xe0800001, // ADD R0, R0, R1
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0xe0822000, // ADD R2, R2, R0
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0xe3822001, // ORR R2, R2, #1
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0xe8bd0003, // LDMFD SP!, {R0,R1}
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0xe12fff12, // BX R2
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0x001007b0, // off_1007EC DCD evp_thunk_template
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0x001007f8, // off_1007F0 DCD thunk_end
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0x40004c30, // off_1007F4 DCD iram_evp_thunks
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// thunk_end is here
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};
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static const u32 evp_thunk_template_len = sizeof(evp_thunk_template);
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// treated as 12bit values
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static const u32 hash_vals[] = {1, 2, 4, 8, 0, 3, 5, 6, 7, 9, 10, 11};
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void fuse_disable_program()
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{
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FUSE(FUSE_DISABLEREGPROGRAM) = 1;
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@ -31,3 +59,291 @@ u32 fuse_read_odm(u32 idx)
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{
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return FUSE(FUSE_RESERVED_ODMX(idx));
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}
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void fuse_wait_idle()
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{
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u32 ctrl;
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do
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{
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ctrl = FUSE(FUSE_CTRL);
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} while (((ctrl >> 16) & 0x1f) != 4);
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}
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u32 fuse_read(u32 addr)
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{
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FUSE(FUSE_ADDR) = addr;
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FUSE(FUSE_CTRL) = (FUSE(FUSE_ADDR) & ~FUSE_CMD_MASK) | FUSE_READ;
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fuse_wait_idle();
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return FUSE(FUSE_RDATA);
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}
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void fuse_read_array(u32 *words)
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{
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for (u32 i = 0; i < 192; i++)
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words[i] = fuse_read(i);
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}
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static u32 _parity32_even(u32 *words, u32 count)
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{
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u32 acc = words[0];
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for (u32 i = 1; i < count; i++)
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{
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acc ^= words[i];
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}
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u32 lo = ((acc & 0xffff) ^ (acc >> 16)) & 0xff;
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u32 hi = ((acc & 0xffff) ^ (acc >> 16)) >> 8;
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u32 x = hi ^ lo;
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lo = ((x & 0xf) ^ (x >> 4)) & 3;
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hi = ((x & 0xf) ^ (x >> 4)) >> 2;
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x = hi ^ lo;
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return (x & 1) ^ (x >> 1);
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}
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static int _patch_hash_one(u32 *word)
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{
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u32 bits20_31 = *word & 0xfff00000;
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u32 parity_bit = _parity32_even(&bits20_31, 1);
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u32 hash = 0;
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for (u32 i = 0; i < 12; i++)
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{
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if (*word & (1 << (20 + i)))
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{
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hash ^= hash_vals[i];
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}
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}
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if (hash == 0)
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{
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if (parity_bit == 0)
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{
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return 0;
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}
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*word ^= 1 << 24;
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return 1;
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}
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if (parity_bit == 0)
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{
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return 3;
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}
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for (u32 i = 0; i < ARRAYSIZE(hash_vals); i++)
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{
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if (hash_vals[i] == hash)
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{
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*word ^= 1 << (20 + i);
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return 1;
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}
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}
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return 2;
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}
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static int _patch_hash_multi(u32 *words, u32 count)
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{
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u32 parity_bit = _parity32_even(words, count);
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u32 bits0_14 = words[0] & 0x7fff;
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u32 bit15 = words[0] & 0x8000;
|
||||
u32 bits16_19 = words[0] & 0xf0000;
|
||||
|
||||
u32 hash = 0;
|
||||
words[0] = bits16_19;
|
||||
for (u32 i = 0; i < count; i++)
|
||||
{
|
||||
u32 w = words[i];
|
||||
if (w)
|
||||
{
|
||||
for (u32 bitpos = 0; bitpos < 32; bitpos++)
|
||||
{
|
||||
if ((w >> bitpos) & 1)
|
||||
{
|
||||
hash ^= 0x4000 + i * 32 + bitpos;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
hash ^= bits0_14;
|
||||
// stupid but this is what original code does.
|
||||
// equivalent to original words[0] &= 0xfff00000
|
||||
words[0] = bits16_19 ^ bit15 ^ bits0_14;
|
||||
|
||||
if (hash == 0)
|
||||
{
|
||||
if (parity_bit == 0)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
words[0] ^= 0x8000;
|
||||
return 1;
|
||||
}
|
||||
if (parity_bit == 0)
|
||||
{
|
||||
return 3;
|
||||
}
|
||||
u32 bitcount = hash - 0x4000;
|
||||
if (bitcount < 16 || bitcount >= count * 32)
|
||||
{
|
||||
u32 num_set = 0;
|
||||
for (u32 bitpos = 0; bitpos < 15; bitpos++)
|
||||
{
|
||||
if ((hash >> bitpos) & 1)
|
||||
{
|
||||
num_set++;
|
||||
}
|
||||
}
|
||||
if (num_set != 1)
|
||||
{
|
||||
return 2;
|
||||
}
|
||||
words[0] ^= hash;
|
||||
return 1;
|
||||
}
|
||||
words[bitcount / 32] ^= 1 << (hash & 0x1f);
|
||||
return 1;
|
||||
}
|
||||
|
||||
int fuse_read_ipatch(void (*ipatch)(u32 offset, u32 value))
|
||||
{
|
||||
u32 words[80];
|
||||
u32 word_count;
|
||||
u32 word_addr;
|
||||
u32 word0 = 0;
|
||||
u32 total_read = 0;
|
||||
|
||||
word_count = FUSE(FUSE_FIRST_BOOTROM_PATCH_SIZE);
|
||||
word_count &= 0x7F;
|
||||
word_addr = 191;
|
||||
|
||||
while (word_count)
|
||||
{
|
||||
total_read += word_count;
|
||||
if (total_read >= ARRAYSIZE(words))
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
for (u32 i = 0; i < word_count; i++)
|
||||
words[i] = fuse_read(word_addr--);
|
||||
|
||||
word0 = words[0];
|
||||
if (_patch_hash_multi(words, word_count) >= 2)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
u32 ipatch_count = (words[0] >> 16) & 0xF;
|
||||
if (ipatch_count)
|
||||
{
|
||||
for (u32 i = 0; i < ipatch_count; i++)
|
||||
{
|
||||
u32 word = words[i + 1];
|
||||
u32 addr = (word >> 16) * 2;
|
||||
u32 data = word & 0xFFFF;
|
||||
|
||||
ipatch(addr, data);
|
||||
}
|
||||
}
|
||||
words[0] = word0;
|
||||
if ((word0 >> 25) == 0)
|
||||
break;
|
||||
if (_patch_hash_one(&word0) >= 2)
|
||||
{
|
||||
return 3;
|
||||
}
|
||||
word_count = word0 >> 25;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int fuse_read_evp_thunk(u32 *iram_evp_thunks, u32 *iram_evp_thunks_len)
|
||||
{
|
||||
u32 words[80];
|
||||
u32 word_count;
|
||||
u32 word_addr;
|
||||
u32 word0 = 0;
|
||||
u32 total_read = 0;
|
||||
int evp_thunk_written = 0;
|
||||
void *evp_thunk_dst_addr = 0;
|
||||
|
||||
memset(iram_evp_thunks, 0, *iram_evp_thunks_len);
|
||||
|
||||
word_count = FUSE(FUSE_FIRST_BOOTROM_PATCH_SIZE);
|
||||
word_count &= 0x7F;
|
||||
word_addr = 191;
|
||||
|
||||
while (word_count)
|
||||
{
|
||||
total_read += word_count;
|
||||
if (total_read >= ARRAYSIZE(words))
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
for (u32 i = 0; i < word_count; i++)
|
||||
words[i] = fuse_read(word_addr--);
|
||||
|
||||
word0 = words[0];
|
||||
if (_patch_hash_multi(words, word_count) >= 2)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
u32 ipatch_count = (words[0] >> 16) & 0xF;
|
||||
u32 insn_count = word_count - ipatch_count - 1;
|
||||
if (insn_count)
|
||||
{
|
||||
if (!evp_thunk_written)
|
||||
{
|
||||
evp_thunk_dst_addr = (void *)iram_evp_thunks;
|
||||
|
||||
memcpy(evp_thunk_dst_addr, (void *)evp_thunk_template, evp_thunk_template_len);
|
||||
evp_thunk_dst_addr += evp_thunk_template_len;
|
||||
evp_thunk_written = 1;
|
||||
*iram_evp_thunks_len = evp_thunk_template_len;
|
||||
|
||||
//write32(TEGRA_EXCEPTION_VECTORS_BASE + 0x208, iram_evp_thunks);
|
||||
}
|
||||
|
||||
u32 thunk_patch_len = insn_count * sizeof(u32);
|
||||
memcpy(evp_thunk_dst_addr, &words[ipatch_count + 1], thunk_patch_len);
|
||||
evp_thunk_dst_addr += thunk_patch_len;
|
||||
*iram_evp_thunks_len += thunk_patch_len;
|
||||
}
|
||||
words[0] = word0;
|
||||
if ((word0 >> 25) == 0)
|
||||
break;
|
||||
if (_patch_hash_one(&word0) >= 2)
|
||||
{
|
||||
return 3;
|
||||
}
|
||||
word_count = word0 >> 25;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool fuse_check_patched_rcm()
|
||||
{
|
||||
// Check if XUSB in use.
|
||||
if (FUSE(FUSE_RESERVED_SW) & (1<<7))
|
||||
return true;
|
||||
|
||||
// Check if RCM is ipatched.
|
||||
u32 word_count = FUSE(FUSE_FIRST_BOOTROM_PATCH_SIZE) & 0x7F;
|
||||
u32 word_addr = 191;
|
||||
|
||||
while (word_count)
|
||||
{
|
||||
u32 word0 = fuse_read(word_addr);
|
||||
u32 ipatch_count = (word0 >> 16) & 0xF;
|
||||
|
||||
for (u32 i = 0; i < ipatch_count; i++)
|
||||
{
|
||||
u32 word = fuse_read(word_addr - (i + 1));
|
||||
u32 addr = (word >> 16) * 2;
|
||||
if (addr == 0x769A)
|
||||
return true;
|
||||
}
|
||||
|
||||
word_addr -= word_count;
|
||||
word_count = word0 >> 25;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -54,6 +54,7 @@
|
|||
#define FUSE_PRIVATE_KEY3 0x1B0
|
||||
#define FUSE_PRIVATE_KEY4 0x1B4
|
||||
#define FUSE_RESERVED_SW 0x1C0
|
||||
#define FUSE_SKU_DIRECT_CONFIG 0x1F4
|
||||
#define FUSE_OPT_VENDOR_CODE 0x200
|
||||
#define FUSE_OPT_FAB_CODE 0x204
|
||||
#define FUSE_OPT_LOT_CODE_0 0x208
|
||||
|
|
@ -74,5 +75,10 @@
|
|||
|
||||
void fuse_disable_program();
|
||||
u32 fuse_read_odm(u32 idx);
|
||||
void fuse_wait_idle();
|
||||
int fuse_read_ipatch(void (*ipatch)(u32 offset, u32 value));
|
||||
int fuse_read_evp_thunk(u32 *iram_evp_thunks, u32 *iram_evp_thunks_len);
|
||||
void fuse_read_array(u32 *words);
|
||||
bool fuse_check_patched_rcm();
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -219,7 +219,7 @@ void _config_regulators()
|
|||
{
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CNFGBBC, MAX77620_CNFGBBC_RESISTOR_1K);
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1,
|
||||
(1 << 6) | (1 << MAX77620_ONOFFCNFG1_MRT_SHIFT)); // PWR delay for forced shutdown off.
|
||||
(1 << 6) | (3 << MAX77620_ONOFFCNFG1_MRT_SHIFT)); // PWR delay for forced shutdown off.
|
||||
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG0,
|
||||
(7 << MAX77620_FPS_TIME_PERIOD_SHIFT));
|
||||
|
|
@ -257,7 +257,7 @@ void _config_regulators()
|
|||
MAX77621_T_JUNCTION_120 | MAX77621_FT_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS |
|
||||
MAX77621_CKKADV_TRIP_150mV_PER_US | MAX77621_INDUCTOR_NOMINAL);
|
||||
|
||||
// Disable low battery shutdown monitor.
|
||||
// Enable low battery shutdown monitor for < 2800mV.
|
||||
max77620_low_battery_monitor_config();
|
||||
}
|
||||
|
||||
|
|
@ -274,6 +274,7 @@ void config_hw()
|
|||
|
||||
// Enable fuse clock.
|
||||
clock_enable_fuse(true);
|
||||
|
||||
// Disable fuse programming.
|
||||
fuse_disable_program();
|
||||
|
||||
|
|
|
|||
|
|
@ -17,7 +17,21 @@
|
|||
#include "../soc/kfuse.h"
|
||||
#include "../soc/clock.h"
|
||||
#include "../soc/t210.h"
|
||||
#include "../utils/util.h"
|
||||
|
||||
#pragma GCC push_options
|
||||
#pragma GCC optimize ("Os")
|
||||
|
||||
int kfuse_wait_ready()
|
||||
{
|
||||
// Wait for KFUSE to finish init and verification of data.
|
||||
while (!(KFUSE(KFUSE_STATE) & KFUSE_STATE_DONE))
|
||||
;
|
||||
|
||||
if (!(KFUSE(KFUSE_STATE) & KFUSE_STATE_CRCPASS))
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int kfuse_read(u32 *buf)
|
||||
{
|
||||
|
|
@ -25,10 +39,7 @@ int kfuse_read(u32 *buf)
|
|||
|
||||
clock_enable_kfuse();
|
||||
|
||||
while (!(KFUSE(KFUSE_STATE) & KFUSE_STATE_DONE))
|
||||
;
|
||||
|
||||
if (!(KFUSE(KFUSE_STATE) & KFUSE_STATE_CRCPASS))
|
||||
if (!kfuse_wait_ready())
|
||||
goto out;
|
||||
|
||||
KFUSE(KFUSE_KEYADDR) = KFUSE_KEYADDR_AUTOINC;
|
||||
|
|
@ -42,16 +53,4 @@ out:;
|
|||
return res;
|
||||
}
|
||||
|
||||
int kfuse_wait_ready()
|
||||
{
|
||||
// Wait for KFUSE to finish init and verification of data.
|
||||
while (!(KFUSE(KFUSE_STATE) & KFUSE_STATE_DONE))
|
||||
{
|
||||
usleep(500);
|
||||
}
|
||||
|
||||
if (!(KFUSE(KFUSE_STATE) & KFUSE_STATE_CRCPASS))
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
#pragma GCC pop_options
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@
|
|||
|
||||
#define KFUSE_NUM_WORDS 144
|
||||
|
||||
int kfuse_read(u32 *buf);
|
||||
int kfuse_wait_ready();
|
||||
int kfuse_read(u32 *buf);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -106,7 +106,7 @@ bool smmu_is_used()
|
|||
|
||||
void smmu_exit()
|
||||
{
|
||||
*(uint32_t *)(smmu_payload + 0x14) = _NOP();
|
||||
*(u32 *)(smmu_payload + 0x14) = _NOP();
|
||||
}
|
||||
|
||||
u32 *smmu_init_domain4(u32 dev_base, u32 asid)
|
||||
|
|
|
|||
|
|
@ -108,6 +108,14 @@
|
|||
|
||||
/*! EVP registers. */
|
||||
#define EVP_CPU_RESET_VECTOR 0x100
|
||||
#define EVP_COP_RESET_VECTOR 0x200
|
||||
#define EVP_COP_UNDEF_VECTOR 0x204
|
||||
#define EVP_COP_SWI_VECTOR 0x208
|
||||
#define EVP_COP_PREFETCH_ABORT_VECTOR 0x20C
|
||||
#define EVP_COP_DATA_ABORT_VECTOR 0x210
|
||||
#define EVP_COP_RSVD_VECTOR 0x214
|
||||
#define EVP_COP_IRQ_VECTOR 0x218
|
||||
#define EVP_COP_FIQ_VECTOR 0x21C
|
||||
|
||||
/*! Misc registers. */
|
||||
#define APB_MISC_PP_STRAPPING_OPT_A 0x08
|
||||
|
|
@ -208,7 +216,7 @@
|
|||
#define HALT_COP_JTAG (1 << 28)
|
||||
#define HALT_COP_WAIT_EVENT (1 << 30)
|
||||
#define HALT_COP_WAIT_IRQ (1 << 31)
|
||||
#define HALT_COP_MAX_CNT 0xFF
|
||||
#define HALT_COP_MAX_CNT 0xFF
|
||||
#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0
|
||||
#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14
|
||||
#define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue