Update to hekate bdk 5.5.6
This commit is contained in:
shchmue
parent
93909f149e
commit
a7712b173c
95 changed files with 2720 additions and 1684 deletions
342
bdk/sec/se.c
342
bdk/sec/se.c
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@ -1,8 +1,8 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018 CTCaer
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* Copyright (c) 2018-2021 CTCaer
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* Copyright (c) 2018 Atmosphère-NX
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* Copyright (c) 2019-2020 shchmue
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* Copyright (c) 2019-2021 shchmue
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -35,8 +35,8 @@ typedef struct _se_ll_t
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vu32 size;
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} se_ll_t;
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static u32 _se_rsa_mod_sizes[TEGRA_SE_RSA_KEYSLOT_COUNT];
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static u32 _se_rsa_exp_sizes[TEGRA_SE_RSA_KEYSLOT_COUNT];
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static u32 _se_rsa_mod_sizes[SE_RSA_KEYSLOT_COUNT];
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static u32 _se_rsa_exp_sizes[SE_RSA_KEYSLOT_COUNT];
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static void _gf256_mul_x(void *block)
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{
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@ -79,17 +79,17 @@ static void _se_ll_init(se_ll_t *ll, u32 addr, u32 size)
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static void _se_ll_set(se_ll_t *dst, se_ll_t *src)
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{
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SE(SE_IN_LL_ADDR_REG_OFFSET) = (u32)src;
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SE(SE_OUT_LL_ADDR_REG_OFFSET) = (u32)dst;
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SE(SE_IN_LL_ADDR_REG) = (u32)src;
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SE(SE_OUT_LL_ADDR_REG) = (u32)dst;
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}
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static int _se_wait()
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{
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while (!(SE(SE_INT_STATUS_REG_OFFSET) & SE_INT_OP_DONE(INT_SET)))
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while (!(SE(SE_INT_STATUS_REG) & SE_INT_OP_DONE))
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;
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if (SE(SE_INT_STATUS_REG_OFFSET) & SE_INT_ERROR(INT_SET) ||
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SE(SE_STATUS_0) & SE_STATUS_0_STATE_WAIT_IN ||
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SE(SE_ERR_STATUS_0) != SE_ERR_STATUS_0_SE_NS_ACCESS_CLEAR)
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if (SE(SE_INT_STATUS_REG) & SE_INT_ERR_STAT ||
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(SE(SE_STATUS_REG) & SE_STATUS_STATE_MASK) != SE_STATUS_STATE_IDLE ||
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SE(SE_ERR_STATUS_REG) != 0)
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return 0;
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return 1;
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}
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@ -114,12 +114,12 @@ static int _se_execute(u32 op, void *dst, u32 dst_size, const void *src, u32 src
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_se_ll_set(ll_dst, ll_src);
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SE(SE_ERR_STATUS_0) = SE(SE_ERR_STATUS_0);
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SE(SE_INT_STATUS_REG_OFFSET) = SE(SE_INT_STATUS_REG_OFFSET);
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SE(SE_ERR_STATUS_REG) = SE(SE_ERR_STATUS_REG);
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SE(SE_INT_STATUS_REG) = SE(SE_INT_STATUS_REG);
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bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false);
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SE(SE_OPERATION_REG_OFFSET) = SE_OPERATION(op);
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SE(SE_OPERATION_REG) = op;
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if (is_oneshot)
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{
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@ -168,13 +168,13 @@ static int _se_execute_one_block(u32 op, void *dst, u32 dst_size, const void *sr
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if (!src || !dst)
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return 0;
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u8 *block = (u8 *)malloc(0x10);
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memset(block, 0, 0x10);
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u8 *block = (u8 *)malloc(SE_AES_BLOCK_SIZE);
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memset(block, 0, SE_AES_BLOCK_SIZE);
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SE(SE_BLOCK_COUNT_REG_OFFSET) = 0;
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SE(SE_CRYPTO_BLOCK_COUNT_REG) = 1 - 1;
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memcpy(block, src, src_size);
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int res = _se_execute_oneshot(op, block, 0x10, block, 0x10);
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int res = _se_execute_oneshot(op, block, SE_AES_BLOCK_SIZE, block, SE_AES_BLOCK_SIZE);
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memcpy(dst, block, dst_size);
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free(block);
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@ -183,21 +183,21 @@ static int _se_execute_one_block(u32 op, void *dst, u32 dst_size, const void *sr
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static void _se_aes_ctr_set(void *ctr)
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{
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u32 data[TEGRA_SE_AES_BLOCK_SIZE / 4];
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memcpy(data, ctr, TEGRA_SE_AES_BLOCK_SIZE);
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u32 data[SE_AES_IV_SIZE / 4];
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memcpy(data, ctr, SE_AES_IV_SIZE);
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for (u32 i = 0; i < (TEGRA_SE_AES_BLOCK_SIZE / 4); i++)
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SE(SE_CRYPTO_CTR_REG_OFFSET + (4 * i)) = data[i];
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for (u32 i = 0; i < SE_CRYPTO_LINEAR_CTR_REG_COUNT; i++)
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SE(SE_CRYPTO_LINEAR_CTR_REG + (4 * i)) = data[i];
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}
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void se_rsa_acc_ctrl(u32 rs, u32 flags)
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{
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if (flags & SE_RSA_KEY_TBL_DIS_KEY_ALL_FLAG)
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SE(SE_RSA_KEYTABLE_ACCESS_REG_OFFSET + 4 * rs) =
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((flags >> SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG_SHIFT) & SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG) |
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((flags & SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_FLAG) ^ SE_RSA_KEY_TBL_DIS_KEY_ALL_COMMON_FLAG);
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if (flags & SE_RSA_KEY_TBL_DIS_KEY_LOCK_FLAG)
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SE(SE_RSA_KEYTABLE_ACCESS_LOCK_OFFSET) &= ~BIT(rs);
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if (flags & SE_RSA_KEY_TBL_DIS_KEY_ACCESS_FLAG)
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SE(SE_RSA_KEYTABLE_ACCESS_REG + 4 * rs) =
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(((flags >> 4) & SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG) |(flags & SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_FLAG)) ^
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SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_USE_FLAG;
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if (flags & SE_RSA_KEY_LOCK_FLAG)
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SE(SE_RSA_SECURITY_PERKEY_REG) &= ~BIT(rs);
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}
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// se_rsa_key_set() was derived from Atmosphère's set_rsa_keyslot
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@ -206,15 +206,15 @@ void se_rsa_key_set(u32 ks, const void *mod, u32 mod_size, const void *exp, u32
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u32 *data = (u32 *)mod;
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for (u32 i = 0; i < mod_size / 4; i++)
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{
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SE(SE_RSA_KEYTABLE_ADDR) = RSA_KEY_NUM(ks) | RSA_KEY_TYPE(RSA_KEY_TYPE_MOD) | i;
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SE(SE_RSA_KEYTABLE_DATA) = byte_swap_32(data[mod_size / 4 - i - 1]);
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SE(SE_RSA_KEYTABLE_ADDR_REG) = RSA_KEY_NUM(ks) | SE_RSA_KEYTABLE_TYPE(RSA_KEY_TYPE_MOD) | i;
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SE(SE_RSA_KEYTABLE_DATA_REG) = byte_swap_32(data[mod_size / 4 - i - 1]);
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}
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data = (u32 *)exp;
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for (u32 i = 0; i < exp_size / 4; i++)
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{
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SE(SE_RSA_KEYTABLE_ADDR) = RSA_KEY_NUM(ks) | RSA_KEY_TYPE(RSA_KEY_TYPE_EXP) | i;
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SE(SE_RSA_KEYTABLE_DATA) = byte_swap_32(data[exp_size / 4 - i - 1]);
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SE(SE_RSA_KEYTABLE_ADDR_REG) = RSA_KEY_NUM(ks) | SE_RSA_KEYTABLE_TYPE(RSA_KEY_TYPE_EXP) | i;
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SE(SE_RSA_KEYTABLE_DATA_REG) = byte_swap_32(data[exp_size / 4 - i - 1]);
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}
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_se_rsa_mod_sizes[ks] = mod_size;
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@ -224,15 +224,15 @@ void se_rsa_key_set(u32 ks, const void *mod, u32 mod_size, const void *exp, u32
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// se_rsa_key_clear() was derived from Atmosphère's clear_rsa_keyslot
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void se_rsa_key_clear(u32 ks)
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{
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for (u32 i = 0; i < TEGRA_SE_RSA2048_DIGEST_SIZE / 4; i++)
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for (u32 i = 0; i < SE_RSA2048_DIGEST_SIZE / 4; i++)
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{
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SE(SE_RSA_KEYTABLE_ADDR) = RSA_KEY_NUM(ks) | RSA_KEY_TYPE(RSA_KEY_TYPE_MOD) | i;
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SE(SE_RSA_KEYTABLE_DATA) = 0;
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SE(SE_RSA_KEYTABLE_ADDR_REG) = RSA_KEY_NUM(ks) | SE_RSA_KEYTABLE_TYPE(RSA_KEY_TYPE_MOD) | i;
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SE(SE_RSA_KEYTABLE_DATA_REG) = 0;
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}
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for (u32 i = 0; i < TEGRA_SE_RSA2048_DIGEST_SIZE / 4; i++)
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for (u32 i = 0; i < SE_RSA2048_DIGEST_SIZE / 4; i++)
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{
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SE(SE_RSA_KEYTABLE_ADDR) = RSA_KEY_NUM(ks) | RSA_KEY_TYPE(RSA_KEY_TYPE_EXP) | i;
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SE(SE_RSA_KEYTABLE_DATA) = 0;
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SE(SE_RSA_KEYTABLE_ADDR_REG) = RSA_KEY_NUM(ks) | SE_RSA_KEYTABLE_TYPE(RSA_KEY_TYPE_EXP) | i;
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SE(SE_RSA_KEYTABLE_DATA_REG) = 0;
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}
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}
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@ -240,22 +240,22 @@ void se_rsa_key_clear(u32 ks)
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int se_rsa_exp_mod(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size)
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{
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int res;
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u8 stack_buf[TEGRA_SE_RSA2048_DIGEST_SIZE];
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u8 stack_buf[SE_RSA2048_DIGEST_SIZE];
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for (u32 i = 0; i < src_size; i++)
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stack_buf[i] = *((u8 *)src + src_size - i - 1);
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SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_ALG(ALG_RSA) | SE_CONFIG_DST(DST_RSAREG);
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SE(SE_CONFIG_REG) = SE_CONFIG_ENC_ALG(ALG_RSA) | SE_CONFIG_DST(DST_RSAREG);
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SE(SE_RSA_CONFIG) = RSA_KEY_SLOT(ks);
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SE(SE_RSA_KEY_SIZE_REG_OFFSET) = (_se_rsa_mod_sizes[ks] >> 6) - 1;
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SE(SE_RSA_EXP_SIZE_REG_OFFSET) = _se_rsa_exp_sizes[ks] >> 2;
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SE(SE_RSA_KEY_SIZE_REG) = (_se_rsa_mod_sizes[ks] >> 6) - 1;
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SE(SE_RSA_EXP_SIZE_REG) = _se_rsa_exp_sizes[ks] >> 2;
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res = _se_execute_oneshot(OP_START, NULL, 0, stack_buf, src_size);
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res = _se_execute_oneshot(SE_OP_START, NULL, 0, stack_buf, src_size);
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// Copy output hash.
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u32 *dst32 = (u32 *)dst;
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for (u32 i = 0; i < dst_size / 4; i++)
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dst32[dst_size / 4 - i - 1] = byte_swap_32(SE(SE_RSA_OUTPUT + (i << 2)));
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dst32[dst_size / 4 - i - 1] = byte_swap_32(SE(SE_RSA_OUTPUT_REG + (i << 2)));
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return res;
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}
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@ -263,54 +263,54 @@ int se_rsa_exp_mod(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_siz
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void se_key_acc_ctrl(u32 ks, u32 flags)
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{
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if (flags & SE_KEY_TBL_DIS_KEY_ACCESS_FLAG)
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SE(SE_KEY_TABLE_ACCESS_REG_OFFSET + 4 * ks) = ~flags;
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if (flags & SE_KEY_TBL_DIS_KEY_LOCK_FLAG)
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SE(SE_KEY_TABLE_ACCESS_LOCK_OFFSET) &= ~BIT(ks);
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SE(SE_CRYPTO_KEYTABLE_ACCESS_REG + 4 * ks) = ~flags;
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if (flags & SE_KEY_LOCK_FLAG)
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SE(SE_CRYPTO_SECURITY_PERKEY_REG) &= ~BIT(ks);
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}
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u32 se_key_acc_ctrl_get(u32 ks)
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{
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return SE(SE_KEY_TABLE_ACCESS_REG_OFFSET + 4 * ks);
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return SE(SE_CRYPTO_KEYTABLE_ACCESS_REG + 4 * ks);
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}
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void se_aes_key_set(u32 ks, const void *key, u32 size)
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{
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u32 data[TEGRA_SE_AES_MAX_KEY_SIZE / 4];
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u32 data[SE_AES_MAX_KEY_SIZE / 4];
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memcpy(data, key, size);
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for (u32 i = 0; i < (size / 4); i++)
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{
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SE(SE_KEYTABLE_REG_OFFSET) = SE_KEYTABLE_SLOT(ks) | i;
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SE(SE_KEYTABLE_DATA0_REG_OFFSET) = data[i];
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SE(SE_CRYPTO_KEYTABLE_ADDR_REG) = SE_KEYTABLE_SLOT(ks) | SE_KEYTABLE_PKT(i); // QUAD is automatically set by PKT.
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SE(SE_CRYPTO_KEYTABLE_DATA_REG) = data[i];
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}
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}
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void se_aes_key_partial_set(u32 ks, u32 index, u32 data)
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{
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SE(SE_KEYTABLE_REG_OFFSET) = SE_KEYTABLE_SLOT(ks) | index;
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SE(SE_KEYTABLE_DATA0_REG_OFFSET) = data;
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SE(SE_CRYPTO_KEYTABLE_ADDR_REG) = SE_KEYTABLE_SLOT(ks) | index;
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SE(SE_CRYPTO_KEYTABLE_DATA_REG) = data;
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}
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void se_aes_iv_set(u32 ks, const void *iv)
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{
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u32 data[TEGRA_SE_AES_BLOCK_SIZE / 4];
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memcpy(data, iv, TEGRA_SE_AES_BLOCK_SIZE);
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u32 data[SE_AES_IV_SIZE / 4];
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memcpy(data, iv, SE_AES_IV_SIZE);
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for (u32 i = 0; i < (TEGRA_SE_AES_BLOCK_SIZE / 4); i++)
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for (u32 i = 0; i < (SE_AES_IV_SIZE / 4); i++)
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{
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SE(SE_KEYTABLE_REG_OFFSET) = SE_KEYTABLE_SLOT(ks) | SE_KEYTABLE_QUAD(QUAD_ORG_IV) | i;
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SE(SE_KEYTABLE_DATA0_REG_OFFSET) = data[i];
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SE(SE_CRYPTO_KEYTABLE_ADDR_REG) = SE_KEYTABLE_SLOT(ks) | SE_KEYTABLE_QUAD(ORIGINAL_IV) | SE_KEYTABLE_PKT(i);
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SE(SE_CRYPTO_KEYTABLE_DATA_REG) = data[i];
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}
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}
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void se_aes_key_get(u32 ks, void *key, u32 size)
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{
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u32 data[TEGRA_SE_AES_MAX_KEY_SIZE / 4];
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u32 data[SE_AES_MAX_KEY_SIZE / 4];
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for (u32 i = 0; i < (size / 4); i++)
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{
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SE(SE_KEYTABLE_REG_OFFSET) = SE_KEYTABLE_SLOT(ks) | i;
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data[i] = SE(SE_KEYTABLE_DATA0_REG_OFFSET);
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SE(SE_CRYPTO_KEYTABLE_ADDR_REG) = SE_KEYTABLE_SLOT(ks) | SE_KEYTABLE_PKT(i); // QUAD is automatically set by PKT.
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data[i] = SE(SE_CRYPTO_KEYTABLE_DATA_REG);
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}
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memcpy(key, data, size);
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@ -318,77 +318,77 @@ void se_aes_key_get(u32 ks, void *key, u32 size)
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void se_aes_key_clear(u32 ks)
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{
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for (u32 i = 0; i < (TEGRA_SE_AES_MAX_KEY_SIZE / 4); i++)
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for (u32 i = 0; i < (SE_AES_MAX_KEY_SIZE / 4); i++)
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{
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SE(SE_KEYTABLE_REG_OFFSET) = SE_KEYTABLE_SLOT(ks) | i;
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SE(SE_KEYTABLE_DATA0_REG_OFFSET) = 0;
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SE(SE_CRYPTO_KEYTABLE_ADDR_REG) = SE_KEYTABLE_SLOT(ks) | SE_KEYTABLE_PKT(i); // QUAD is automatically set by PKT.
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SE(SE_CRYPTO_KEYTABLE_DATA_REG) = 0;
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}
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}
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void se_aes_iv_clear(u32 ks)
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{
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for (u32 i = 0; i < (TEGRA_SE_AES_BLOCK_SIZE / 4); i++)
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for (u32 i = 0; i < (SE_AES_IV_SIZE / 4); i++)
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{
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SE(SE_KEYTABLE_REG_OFFSET) = SE_KEYTABLE_SLOT(ks) | SE_KEYTABLE_QUAD(QUAD_ORG_IV) | i;
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SE(SE_KEYTABLE_DATA0_REG_OFFSET) = 0;
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SE(SE_CRYPTO_KEYTABLE_ADDR_REG) = SE_KEYTABLE_SLOT(ks) | SE_KEYTABLE_QUAD(ORIGINAL_IV) | SE_KEYTABLE_PKT(i);
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SE(SE_CRYPTO_KEYTABLE_DATA_REG) = 0;
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}
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}
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int se_aes_unwrap_key(u32 ks_dst, u32 ks_src, const void *input)
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{
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SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_KEYTAB);
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SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks_src) | SE_CRYPTO_CORE_SEL(CORE_DECRYPT);
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SE(SE_BLOCK_COUNT_REG_OFFSET) = 0;
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SE(SE_CRYPTO_KEYTABLE_DST_REG_OFFSET) = SE_CRYPTO_KEYTABLE_DST_KEY_INDEX(ks_dst);
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SE(SE_CONFIG_REG) = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_KEYTABLE);
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SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks_src) | SE_CRYPTO_CORE_SEL(CORE_DECRYPT);
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SE(SE_CRYPTO_BLOCK_COUNT_REG) = 1 - 1;
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SE(SE_CRYPTO_KEYTABLE_DST_REG) = SE_KEYTABLE_DST_KEY_INDEX(ks_dst) | SE_KEYTABLE_DST_WORD_QUAD(KEYS_0_3);
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return _se_execute_oneshot(OP_START, NULL, 0, input, 0x10);
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return _se_execute_oneshot(SE_OP_START, NULL, 0, input, SE_KEY_128_SIZE);
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}
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int se_aes_crypt_ecb(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size)
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{
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if (enc)
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{
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SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY);
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SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT);
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SE(SE_CONFIG_REG) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY);
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SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT);
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}
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else
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{
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SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_MEMORY);
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SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_CORE_SEL(CORE_DECRYPT);
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SE(SE_CONFIG_REG) = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_MEMORY);
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SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_CORE_SEL(CORE_DECRYPT);
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}
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SE(SE_BLOCK_COUNT_REG_OFFSET) = (src_size >> 4) - 1;
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return _se_execute_oneshot(OP_START, dst, dst_size, src, src_size);
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SE(SE_CRYPTO_BLOCK_COUNT_REG) = (src_size >> 4) - 1;
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return _se_execute_oneshot(SE_OP_START, dst, dst_size, src, src_size);
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}
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|
||||
int se_aes_crypt_cbc(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size)
|
||||
{
|
||||
if (enc)
|
||||
{
|
||||
SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY);
|
||||
SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_AESOUT) |
|
||||
SE(SE_CONFIG_REG) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY);
|
||||
SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_AESOUT) |
|
||||
SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_XOR_POS(XOR_TOP);
|
||||
}
|
||||
else
|
||||
{
|
||||
SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_MEMORY);
|
||||
SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_PREVAHB) |
|
||||
SE(SE_CONFIG_REG) = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_MEMORY);
|
||||
SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_PREVMEM) |
|
||||
SE_CRYPTO_CORE_SEL(CORE_DECRYPT) | SE_CRYPTO_XOR_POS(XOR_BOTTOM);
|
||||
}
|
||||
SE(SE_BLOCK_COUNT_REG_OFFSET) = (src_size >> 4) - 1;
|
||||
return _se_execute_oneshot(OP_START, dst, dst_size, src, src_size);
|
||||
SE(SE_CRYPTO_BLOCK_COUNT_REG) = (src_size >> 4) - 1;
|
||||
return _se_execute_oneshot(SE_OP_START, dst, dst_size, src, src_size);
|
||||
}
|
||||
|
||||
int se_aes_crypt_block_ecb(u32 ks, u32 enc, void *dst, const void *src)
|
||||
{
|
||||
return se_aes_crypt_ecb(ks, enc, dst, 0x10, src, 0x10);
|
||||
return se_aes_crypt_ecb(ks, enc, dst, SE_AES_BLOCK_SIZE, src, SE_AES_BLOCK_SIZE);
|
||||
}
|
||||
|
||||
int se_aes_crypt_ctr(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size, void *ctr)
|
||||
{
|
||||
SE(SE_SPARE_0_REG_OFFSET) = 1;
|
||||
SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY);
|
||||
SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) |
|
||||
SE_CRYPTO_XOR_POS(XOR_BOTTOM) | SE_CRYPTO_INPUT_SEL(INPUT_LNR_CTR) | SE_CRYPTO_CTR_VAL(1);
|
||||
SE(SE_SPARE_REG) = SE_ECO(SE_ERRATA_FIX_ENABLE);
|
||||
SE(SE_CONFIG_REG) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY);
|
||||
SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) |
|
||||
SE_CRYPTO_XOR_POS(XOR_BOTTOM) | SE_CRYPTO_INPUT_SEL(INPUT_LNR_CTR) | SE_CRYPTO_CTR_CNTN(1);
|
||||
_se_aes_ctr_set(ctr);
|
||||
|
||||
u32 src_size_aligned = src_size & 0xFFFFFFF0;
|
||||
|
|
@ -396,13 +396,13 @@ int se_aes_crypt_ctr(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_s
|
|||
|
||||
if (src_size_aligned)
|
||||
{
|
||||
SE(SE_BLOCK_COUNT_REG_OFFSET) = (src_size >> 4) - 1;
|
||||
if (!_se_execute_oneshot(OP_START, dst, dst_size, src, src_size_aligned))
|
||||
SE(SE_CRYPTO_BLOCK_COUNT_REG) = (src_size >> 4) - 1;
|
||||
if (!_se_execute_oneshot(SE_OP_START, dst, dst_size, src, src_size_aligned))
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (src_size - src_size_aligned && src_size_aligned < dst_size)
|
||||
return _se_execute_one_block(OP_START, dst + src_size_aligned,
|
||||
return _se_execute_one_block(SE_OP_START, dst + src_size_aligned,
|
||||
MIN(src_size_delta, dst_size - src_size_aligned),
|
||||
src + src_size_aligned, src_size_delta);
|
||||
|
||||
|
|
@ -419,15 +419,15 @@ int se_initialize_rng()
|
|||
|
||||
u8 *output_buf = (u8 *)malloc(0x10);
|
||||
|
||||
SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_MEMORY);
|
||||
SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_INPUT_SEL(INPUT_RANDOM);
|
||||
SE(SE_RNG_CONFIG_REG_OFFSET) = SE_RNG_CONFIG_MODE(RNG_MODE_FORCE_INSTANTION) | SE_RNG_CONFIG_SRC(RNG_SRC_ENTROPY);
|
||||
SE(SE_RNG_RESEED_INTERVAL_REG_OFFSET) = 70001;
|
||||
SE(SE_RNG_SRC_CONFIG_REG_OFFSET) = SE_RNG_SRC_CONFIG_ENT_SRC(RNG_SRC_RO_ENT_ENABLE) |
|
||||
SE_RNG_SRC_CONFIG_ENT_SRC_LOCK(RNG_SRC_RO_ENT_LOCK_ENABLE);
|
||||
SE(SE_BLOCK_COUNT_REG_OFFSET) = 0;
|
||||
SE(SE_CONFIG_REG) = SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_MEMORY);
|
||||
SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_INPUT_SEL(INPUT_RANDOM);
|
||||
SE(SE_RNG_CONFIG_REG) = SE_RNG_CONFIG_MODE(MODE_FORCE_INSTANTION) | SE_RNG_CONFIG_SRC(SRC_ENTROPY);
|
||||
SE(SE_RNG_RESEED_INTERVAL_REG) = 70001;
|
||||
SE(SE_RNG_SRC_CONFIG_REG) = SE_RNG_SRC_CONFIG_ENTR_SRC(RO_ENTR_ENABLE) |
|
||||
SE_RNG_SRC_CONFIG_ENTR_SRC_LOCK(RO_ENTR_LOCK_ENABLE);
|
||||
SE(SE_CRYPTO_BLOCK_COUNT_REG) = 0;
|
||||
|
||||
int res =_se_execute_oneshot(OP_START, output_buf, 0x10, NULL, 0);
|
||||
int res =_se_execute_oneshot(SE_OP_START, output_buf, 0x10, NULL, 0);
|
||||
|
||||
free(output_buf);
|
||||
if (res)
|
||||
|
|
@ -437,35 +437,35 @@ int se_initialize_rng()
|
|||
|
||||
int se_generate_random(void *dst, u32 size)
|
||||
{
|
||||
SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_MEMORY);
|
||||
SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_INPUT_SEL(INPUT_RANDOM);
|
||||
SE(SE_RNG_CONFIG_REG_OFFSET) = SE_RNG_CONFIG_MODE(RNG_MODE_NORMAL) | SE_RNG_CONFIG_SRC(RNG_SRC_ENTROPY);
|
||||
SE(SE_CONFIG_REG) = SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_MEMORY);
|
||||
SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_INPUT_SEL(INPUT_RANDOM);
|
||||
SE(SE_RNG_CONFIG_REG) = SE_RNG_CONFIG_MODE(MODE_NORMAL) | SE_RNG_CONFIG_SRC(SRC_ENTROPY);
|
||||
|
||||
u32 num_blocks = size >> 4;
|
||||
u32 aligned_size = num_blocks << 4;
|
||||
if (num_blocks)
|
||||
{
|
||||
SE(SE_BLOCK_COUNT_REG_OFFSET) = num_blocks - 1;
|
||||
if (!_se_execute_oneshot(OP_START, dst, aligned_size, NULL, 0))
|
||||
SE(SE_CRYPTO_BLOCK_COUNT_REG) = num_blocks - 1;
|
||||
if (!_se_execute_oneshot(SE_OP_START, dst, aligned_size, NULL, 0))
|
||||
return 0;
|
||||
}
|
||||
if (size > aligned_size)
|
||||
return _se_execute_one_block(OP_START, dst + aligned_size, size - aligned_size, NULL, 0);
|
||||
return _se_execute_one_block(SE_OP_START, dst + aligned_size, size - aligned_size, NULL, 0);
|
||||
return 1;
|
||||
}
|
||||
|
||||
int se_generate_random_key(u32 ks_dst, u32 ks_src)
|
||||
{
|
||||
SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_MEMORY);
|
||||
SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks_src) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) |
|
||||
SE(SE_CONFIG_REG) = SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_MEMORY);
|
||||
SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks_src) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) |
|
||||
SE_CRYPTO_INPUT_SEL(INPUT_RANDOM);
|
||||
SE(SE_RNG_CONFIG_REG_OFFSET) = SE_RNG_CONFIG_MODE(RNG_MODE_NORMAL) | SE_RNG_CONFIG_SRC(RNG_SRC_ENTROPY);
|
||||
SE(SE_RNG_CONFIG_REG) = SE_RNG_CONFIG_MODE(MODE_NORMAL) | SE_RNG_CONFIG_SRC(SRC_ENTROPY);
|
||||
|
||||
SE(SE_CRYPTO_KEYTABLE_DST_REG_OFFSET) = SE_CRYPTO_KEYTABLE_DST_KEY_INDEX(ks_dst);
|
||||
if (!_se_execute_oneshot(OP_START, NULL, 0, NULL, 0))
|
||||
SE(SE_CRYPTO_KEYTABLE_DST_REG) = SE_KEYTABLE_DST_KEY_INDEX(ks_dst);
|
||||
if (!_se_execute_oneshot(SE_OP_START, NULL, 0, NULL, 0))
|
||||
return 0;
|
||||
SE(SE_CRYPTO_KEYTABLE_DST_REG_OFFSET) = SE_CRYPTO_KEYTABLE_DST_KEY_INDEX(ks_dst) | 1;
|
||||
if (!_se_execute_oneshot(OP_START, NULL, 0, NULL, 0))
|
||||
SE(SE_CRYPTO_KEYTABLE_DST_REG) = SE_KEYTABLE_DST_KEY_INDEX(ks_dst) | 1;
|
||||
if (!_se_execute_oneshot(SE_OP_START, NULL, 0, NULL, 0))
|
||||
return 0;
|
||||
|
||||
return 1;
|
||||
|
|
@ -544,8 +544,8 @@ int se_aes_cmac(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size)
|
|||
if (src_size & 0xF)
|
||||
_gf256_mul_x(key);
|
||||
|
||||
SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_HASHREG);
|
||||
SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_INPUT_SEL(INPUT_AHB) |
|
||||
SE(SE_CONFIG_REG) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_HASHREG);
|
||||
SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_INPUT_SEL(INPUT_MEMORY) |
|
||||
SE_CRYPTO_XOR_POS(XOR_TOP) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_AESOUT) | SE_CRYPTO_HASH(HASH_ENABLE) |
|
||||
SE_CRYPTO_CORE_SEL(CORE_ENCRYPT);
|
||||
se_aes_iv_clear(ks);
|
||||
|
|
@ -553,10 +553,10 @@ int se_aes_cmac(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size)
|
|||
u32 num_blocks = (src_size + 0xf) >> 4;
|
||||
if (num_blocks > 1)
|
||||
{
|
||||
SE(SE_BLOCK_COUNT_REG_OFFSET) = num_blocks - 2;
|
||||
if (!_se_execute_oneshot(OP_START, NULL, 0, src, src_size))
|
||||
SE(SE_CRYPTO_BLOCK_COUNT_REG) = num_blocks - 2;
|
||||
if (!_se_execute_oneshot(SE_OP_START, NULL, 0, src, src_size))
|
||||
goto out;
|
||||
SE(SE_CRYPTO_REG_OFFSET) |= SE_CRYPTO_IV_SEL(IV_UPDATED);
|
||||
SE(SE_CRYPTO_CONFIG_REG) |= SE_CRYPTO_IV_SEL(IV_UPDATED);
|
||||
}
|
||||
|
||||
if (src_size & 0xf)
|
||||
|
|
@ -572,12 +572,12 @@ int se_aes_cmac(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size)
|
|||
for (u32 i = 0; i < 0x10; i++)
|
||||
last_block[i] ^= key[i];
|
||||
|
||||
SE(SE_BLOCK_COUNT_REG_OFFSET) = 0;
|
||||
res = _se_execute_oneshot(OP_START, NULL, 0, last_block, 0x10);
|
||||
SE(SE_CRYPTO_BLOCK_COUNT_REG) = 0;
|
||||
res = _se_execute_oneshot(SE_OP_START, NULL, 0, last_block, 0x10);
|
||||
|
||||
u32 *dst32 = (u32 *)dst;
|
||||
for (u32 i = 0; i < (dst_size >> 2); i++)
|
||||
dst32[i] = SE(SE_HASH_RESULT_REG_OFFSET + (i << 2));
|
||||
dst32[i] = SE(SE_HASH_RESULT_REG + (i << 2));
|
||||
|
||||
out:;
|
||||
free(key);
|
||||
|
|
@ -588,62 +588,62 @@ out:;
|
|||
int se_calc_sha256(void *hash, u32 *msg_left, const void *src, u32 src_size, u64 total_size, u32 sha_cfg, bool is_oneshot)
|
||||
{
|
||||
int res;
|
||||
u32 hash32[TEGRA_SE_SHA_256_SIZE / 4];
|
||||
u32 hash32[SE_SHA_256_SIZE / 4];
|
||||
|
||||
//! TODO: src_size must be 512 bit aligned if continuing and not last block for SHA256.
|
||||
if (src_size > 0xFFFFFF || !hash) // Max 16MB - 1 chunks and aligned x4 hash buffer.
|
||||
return 0;
|
||||
|
||||
// Setup config for SHA256.
|
||||
SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_MODE(MODE_SHA256) | SE_CONFIG_ENC_ALG(ALG_SHA) | SE_CONFIG_DST(DST_HASHREG);
|
||||
SE(SE_SHA_CONFIG_REG_OFFSET) = sha_cfg;
|
||||
SE(SE_BLOCK_COUNT_REG_OFFSET) = 0;
|
||||
SE(SE_CONFIG_REG) = SE_CONFIG_ENC_MODE(MODE_SHA256) | SE_CONFIG_ENC_ALG(ALG_SHA) | SE_CONFIG_DST(DST_HASHREG);
|
||||
SE(SE_SHA_CONFIG_REG) = sha_cfg;
|
||||
SE(SE_CRYPTO_BLOCK_COUNT_REG) = 1 - 1;
|
||||
|
||||
// Set total size to current buffer size if empty.
|
||||
if (!total_size)
|
||||
total_size = src_size;
|
||||
|
||||
// Set total size: BITS(src_size), up to 2 EB.
|
||||
SE(SE_SHA_MSG_LENGTH_0_REG_OFFSET) = (u32)(total_size << 3);
|
||||
SE(SE_SHA_MSG_LENGTH_1_REG_OFFSET) = (u32)(total_size >> 29);
|
||||
SE(SE_SHA_MSG_LENGTH_2_REG_OFFSET) = 0;
|
||||
SE(SE_SHA_MSG_LENGTH_3_REG_OFFSET) = 0;
|
||||
SE(SE_SHA_MSG_LENGTH_0_REG) = (u32)(total_size << 3);
|
||||
SE(SE_SHA_MSG_LENGTH_1_REG) = (u32)(total_size >> 29);
|
||||
SE(SE_SHA_MSG_LENGTH_2_REG) = 0;
|
||||
SE(SE_SHA_MSG_LENGTH_3_REG) = 0;
|
||||
|
||||
// Set size left to hash.
|
||||
SE(SE_SHA_MSG_LEFT_0_REG_OFFSET) = (u32)(total_size << 3);
|
||||
SE(SE_SHA_MSG_LEFT_1_REG_OFFSET) = (u32)(total_size >> 29);
|
||||
SE(SE_SHA_MSG_LEFT_2_REG_OFFSET) = 0;
|
||||
SE(SE_SHA_MSG_LEFT_3_REG_OFFSET) = 0;
|
||||
SE(SE_SHA_MSG_LEFT_0_REG) = (u32)(total_size << 3);
|
||||
SE(SE_SHA_MSG_LEFT_1_REG) = (u32)(total_size >> 29);
|
||||
SE(SE_SHA_MSG_LEFT_2_REG) = 0;
|
||||
SE(SE_SHA_MSG_LEFT_3_REG) = 0;
|
||||
|
||||
// If we hash in chunks, copy over the intermediate.
|
||||
if (sha_cfg == SHA_CONTINUE && msg_left)
|
||||
{
|
||||
// Restore message left to process.
|
||||
SE(SE_SHA_MSG_LEFT_0_REG_OFFSET) = msg_left[0];
|
||||
SE(SE_SHA_MSG_LEFT_1_REG_OFFSET) = msg_left[1];
|
||||
SE(SE_SHA_MSG_LEFT_0_REG) = msg_left[0];
|
||||
SE(SE_SHA_MSG_LEFT_1_REG) = msg_left[1];
|
||||
|
||||
// Restore hash reg.
|
||||
memcpy(hash32, hash, TEGRA_SE_SHA_256_SIZE);
|
||||
for (u32 i = 0; i < (TEGRA_SE_SHA_256_SIZE / 4); i++)
|
||||
SE(SE_HASH_RESULT_REG_OFFSET + (i << 2)) = byte_swap_32(hash32[i]);
|
||||
memcpy(hash32, hash, SE_SHA_256_SIZE);
|
||||
for (u32 i = 0; i < (SE_SHA_256_SIZE / 4); i++)
|
||||
SE(SE_HASH_RESULT_REG + (i * 4)) = byte_swap_32(hash32[i]);
|
||||
}
|
||||
|
||||
// Trigger the operation.
|
||||
res = _se_execute(OP_START, NULL, 0, src, src_size, is_oneshot);
|
||||
res = _se_execute(SE_OP_START, NULL, 0, src, src_size, is_oneshot);
|
||||
|
||||
if (is_oneshot)
|
||||
{
|
||||
// Backup message left.
|
||||
if (msg_left)
|
||||
{
|
||||
msg_left[0] = SE(SE_SHA_MSG_LEFT_0_REG_OFFSET);
|
||||
msg_left[1] = SE(SE_SHA_MSG_LEFT_1_REG_OFFSET);
|
||||
msg_left[0] = SE(SE_SHA_MSG_LEFT_0_REG);
|
||||
msg_left[1] = SE(SE_SHA_MSG_LEFT_1_REG);
|
||||
}
|
||||
|
||||
// Copy output hash.
|
||||
for (u32 i = 0; i < (TEGRA_SE_SHA_256_SIZE / 4); i++)
|
||||
hash32[i] = byte_swap_32(SE(SE_HASH_RESULT_REG_OFFSET + (i << 2)));
|
||||
memcpy(hash, hash32, TEGRA_SE_SHA_256_SIZE);
|
||||
for (u32 i = 0; i < (SE_SHA_256_SIZE / 4); i++)
|
||||
hash32[i] = byte_swap_32(SE(SE_HASH_RESULT_REG + (i * 4)));
|
||||
memcpy(hash, hash32, SE_SHA_256_SIZE);
|
||||
}
|
||||
|
||||
return res;
|
||||
|
|
@ -656,20 +656,20 @@ int se_calc_sha256_oneshot(void *hash, const void *src, u32 src_size)
|
|||
|
||||
int se_calc_sha256_finalize(void *hash, u32 *msg_left)
|
||||
{
|
||||
u32 hash32[TEGRA_SE_SHA_256_SIZE / 4];
|
||||
u32 hash32[SE_SHA_256_SIZE / 4];
|
||||
int res = _se_execute_finalize();
|
||||
|
||||
// Backup message left.
|
||||
if (msg_left)
|
||||
{
|
||||
msg_left[0] = SE(SE_SHA_MSG_LEFT_0_REG_OFFSET);
|
||||
msg_left[1] = SE(SE_SHA_MSG_LEFT_1_REG_OFFSET);
|
||||
msg_left[0] = SE(SE_SHA_MSG_LEFT_0_REG);
|
||||
msg_left[1] = SE(SE_SHA_MSG_LEFT_1_REG);
|
||||
}
|
||||
|
||||
// Copy output hash.
|
||||
for (u32 i = 0; i < (TEGRA_SE_SHA_256_SIZE / 4); i++)
|
||||
hash32[i] = byte_swap_32(SE(SE_HASH_RESULT_REG_OFFSET + (i << 2)));
|
||||
memcpy(hash, hash32, TEGRA_SE_SHA_256_SIZE);
|
||||
for (u32 i = 0; i < (SE_SHA_256_SIZE / 4); i++)
|
||||
hash32[i] = byte_swap_32(SE(SE_HASH_RESULT_REG + (i << 2)));
|
||||
memcpy(hash, hash32, SE_SHA_256_SIZE);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
|
@ -793,43 +793,43 @@ void se_get_aes_keys(u8 *buf, u8 *keys, u32 keysize)
|
|||
u8 *aligned_buf = (u8 *)ALIGN((u32)buf, 0x40);
|
||||
|
||||
// Set Secure Random Key.
|
||||
SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_MODE(MODE_KEY128) | SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_SRK);
|
||||
SE(SE_CRYPTO_REG_OFFSET) = SE_CRYPTO_KEY_INDEX(0) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_INPUT_SEL(INPUT_RANDOM);
|
||||
SE(SE_RNG_CONFIG_REG_OFFSET) = SE_RNG_CONFIG_SRC(RNG_SRC_ENTROPY) | SE_RNG_CONFIG_MODE(RNG_MODE_FORCE_RESEED);
|
||||
SE(SE_CONFIG_REG) = SE_CONFIG_ENC_MODE(MODE_KEY128) | SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_SRK);
|
||||
SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(0) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_INPUT_SEL(INPUT_RANDOM);
|
||||
SE(SE_RNG_CONFIG_REG) = SE_RNG_CONFIG_SRC(SRC_ENTROPY) | SE_RNG_CONFIG_MODE(MODE_FORCE_RESEED);
|
||||
SE(SE_CRYPTO_LAST_BLOCK) = 0;
|
||||
_se_execute_oneshot(OP_START, NULL, 0, NULL, 0);
|
||||
_se_execute_oneshot(SE_OP_START, NULL, 0, NULL, 0);
|
||||
|
||||
// Save AES keys.
|
||||
SE(SE_CONFIG_REG_OFFSET) = SE_CONFIG_ENC_MODE(MODE_KEY128) | SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY);
|
||||
SE(SE_CONFIG_REG) = SE_CONFIG_ENC_MODE(MODE_KEY128) | SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY);
|
||||
|
||||
for (u32 i = 0; i < TEGRA_SE_KEYSLOT_COUNT; i++)
|
||||
for (u32 i = 0; i < SE_AES_KEYSLOT_COUNT; i++)
|
||||
{
|
||||
SE(SE_CONTEXT_SAVE_CONFIG_REG_OFFSET) = SE_CONTEXT_SAVE_SRC(AES_KEYTABLE) |
|
||||
(i << SE_KEY_INDEX_SHIFT) | SE_CONTEXT_SAVE_WORD_QUAD(KEYS_0_3);
|
||||
SE(SE_CONTEXT_SAVE_CONFIG_REG) = SE_CONTEXT_SRC(AES_KEYTABLE) | SE_KEYTABLE_DST_KEY_INDEX(i) |
|
||||
SE_CONTEXT_AES_KEY_INDEX(0) | SE_CONTEXT_AES_WORD_QUAD(KEYS_0_3);
|
||||
|
||||
SE(SE_CRYPTO_LAST_BLOCK) = 0;
|
||||
_se_execute_oneshot(OP_CTX_SAVE, aligned_buf, 0x10, NULL, 0);
|
||||
memcpy(keys + i * keysize, aligned_buf, 0x10);
|
||||
_se_execute_oneshot(SE_OP_CTX_SAVE, aligned_buf, SE_AES_BLOCK_SIZE, NULL, 0);
|
||||
memcpy(keys + i * keysize, aligned_buf, SE_AES_BLOCK_SIZE);
|
||||
|
||||
if (keysize > 0x10)
|
||||
if (keysize > SE_KEY_128_SIZE)
|
||||
{
|
||||
SE(SE_CONTEXT_SAVE_CONFIG_REG_OFFSET) = SE_CONTEXT_SAVE_SRC(AES_KEYTABLE) |
|
||||
(i << SE_KEY_INDEX_SHIFT) | SE_CONTEXT_SAVE_WORD_QUAD(KEYS_4_7);
|
||||
SE(SE_CONTEXT_SAVE_CONFIG_REG) = SE_CONTEXT_SRC(AES_KEYTABLE) | SE_KEYTABLE_DST_KEY_INDEX(i) |
|
||||
SE_CONTEXT_AES_KEY_INDEX(0) | SE_CONTEXT_AES_WORD_QUAD(KEYS_4_7);
|
||||
|
||||
SE(SE_CRYPTO_LAST_BLOCK) = 0;
|
||||
_se_execute_oneshot(OP_CTX_SAVE, aligned_buf, 0x10, NULL, 0);
|
||||
memcpy(keys + i * keysize + 0x10, aligned_buf, 0x10);
|
||||
_se_execute_oneshot(SE_OP_CTX_SAVE, aligned_buf, SE_AES_BLOCK_SIZE, NULL, 0);
|
||||
memcpy(keys + i * keysize + SE_AES_BLOCK_SIZE, aligned_buf, SE_AES_BLOCK_SIZE);
|
||||
}
|
||||
}
|
||||
|
||||
// Save SRK to PMC secure scratches.
|
||||
SE(SE_CONTEXT_SAVE_CONFIG_REG_OFFSET) = SE_CONTEXT_SAVE_SRC(SRK);
|
||||
SE(SE_CRYPTO_LAST_BLOCK) = 0;
|
||||
_se_execute_oneshot(OP_CTX_SAVE, NULL, 0, NULL, 0);
|
||||
SE(SE_CONTEXT_SAVE_CONFIG_REG) = SE_CONTEXT_SRC(SRK);
|
||||
SE(SE_CRYPTO_LAST_BLOCK) = 0;
|
||||
_se_execute_oneshot(SE_OP_CTX_SAVE, NULL, 0, NULL, 0);
|
||||
|
||||
// End context save.
|
||||
SE(SE_CONFIG_REG_OFFSET) = 0;
|
||||
_se_execute_oneshot(OP_CTX_SAVE, NULL, 0, NULL, 0);
|
||||
SE(SE_CONFIG_REG) = 0;
|
||||
_se_execute_oneshot(SE_OP_CTX_SAVE, NULL, 0, NULL, 0);
|
||||
|
||||
// Get SRK.
|
||||
u32 srk[4];
|
||||
|
|
@ -840,7 +840,7 @@ void se_get_aes_keys(u8 *buf, u8 *keys, u32 keysize)
|
|||
|
||||
// Decrypt context.
|
||||
se_aes_key_clear(3);
|
||||
se_aes_key_set(3, srk, 0x10);
|
||||
se_aes_crypt_cbc(3, 0, keys, TEGRA_SE_KEYSLOT_COUNT * keysize, keys, TEGRA_SE_KEYSLOT_COUNT * keysize);
|
||||
se_aes_key_set(3, srk, SE_KEY_128_SIZE);
|
||||
se_aes_crypt_cbc(3, 0, keys, SE_AES_KEYSLOT_COUNT * keysize, keys, SE_AES_KEYSLOT_COUNT * keysize);
|
||||
se_aes_key_clear(3);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,7 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2019-2021 CTCaer
|
||||
* Copyright (c) 2019-2021 shchmue
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
|
|
@ -25,6 +27,7 @@ void se_rsa_key_clear(u32 ks);
|
|||
int se_rsa_exp_mod(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size);
|
||||
void se_key_acc_ctrl(u32 ks, u32 flags);
|
||||
u32 se_key_acc_ctrl_get(u32 ks);
|
||||
void se_get_aes_keys(u8 *buf, u8 *keys, u32 keysize);
|
||||
void se_aes_key_set(u32 ks, const void *key, u32 size);
|
||||
void se_aes_iv_set(u32 ks, const void *iv);
|
||||
void se_aes_key_partial_set(u32 ks, u32 index, u32 data);
|
||||
|
|
@ -35,10 +38,10 @@ int se_initialize_rng();
|
|||
int se_generate_random(void *dst, u32 size);
|
||||
int se_generate_random_key(u32 ks_dst, u32 ks_src);
|
||||
int se_aes_unwrap_key(u32 ks_dst, u32 ks_src, const void *input);
|
||||
int se_aes_crypt_cbc(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size);
|
||||
int se_aes_crypt_ecb(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size);
|
||||
int se_aes_crypt_block_ecb(u32 ks, u32 enc, void *dst, const void *src);
|
||||
int se_aes_crypt_ctr(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size, void *ctr);
|
||||
int se_aes_crypt_cbc(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size);
|
||||
int se_aes_xts_crypt_sec(u32 tweak_ks, u32 crypt_ks, u32 enc, u64 sec, void *dst, const void *src, u32 sec_size);
|
||||
int se_aes_xts_crypt(u32 tweak_ks, u32 crypt_ks, u32 enc, u64 sec, void *dst, const void *src, u32 sec_size, u32 num_secs);
|
||||
int se_aes_cmac(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size);
|
||||
|
|
@ -47,6 +50,5 @@ int se_calc_sha256_oneshot(void *hash, const void *src, u32 src_size);
|
|||
int se_calc_sha256_finalize(void *hash, u32 *msg_left);
|
||||
int se_calc_hmac_sha256(void *dst, const void *src, u32 src_size, const void *key, u32 key_size);
|
||||
u32 se_rsa_oaep_decode(void *dst, u32 dst_size, const void *label_digest, u32 label_digest_size, u8 *buf, u32 buf_size);
|
||||
void se_get_aes_keys(u8 *buf, u8 *keys, u32 keysize);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,400 +1,323 @@
|
|||
/*
|
||||
* Driver for Tegra Security Engine
|
||||
*
|
||||
* Copyright (c) 2011-2013, NVIDIA Corporation. All Rights Reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
|
||||
*/
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018-2021 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _CRYPTO_TEGRA_SE_H
|
||||
#define _CRYPTO_TEGRA_SE_H
|
||||
#ifndef _SE_T210_H
|
||||
#define _SE_T210_H
|
||||
|
||||
#include <utils/types.h>
|
||||
|
||||
#define TEGRA_SE_CRA_PRIORITY 300
|
||||
#define TEGRA_SE_COMPOSITE_PRIORITY 400
|
||||
#define TEGRA_SE_CRYPTO_QUEUE_LENGTH 50
|
||||
#define SE_MAX_SRC_SG_COUNT 50
|
||||
#define SE_MAX_DST_SG_COUNT 50
|
||||
#define SE_CRYPTO_QUEUE_LENGTH 50
|
||||
#define SE_MAX_SRC_SG_COUNT 50
|
||||
#define SE_MAX_DST_SG_COUNT 50
|
||||
|
||||
#define TEGRA_SE_KEYSLOT_COUNT 16
|
||||
#define SE_MAX_LAST_BLOCK_SIZE 0xFFFFF
|
||||
#define SE_AES_KEYSLOT_COUNT 16
|
||||
#define SE_RSA_KEYSLOT_COUNT 2
|
||||
#define SE_MAX_LAST_BLOCK_SIZE 0xFFFFF
|
||||
|
||||
#define SE_AES_BLOCK_SIZE 16
|
||||
#define SE_AES_IV_SIZE 16
|
||||
#define SE_AES_MIN_KEY_SIZE 16
|
||||
#define SE_AES_MAX_KEY_SIZE 32
|
||||
#define SE_KEY_128_SIZE 16
|
||||
#define SE_KEY_192_SIZE 24
|
||||
#define SE_KEY_256_SIZE 32
|
||||
#define SE_SHA_192_SIZE 24
|
||||
#define SE_SHA_256_SIZE 32
|
||||
#define SE_SHA_384_SIZE 48
|
||||
#define SE_SHA_512_SIZE 64
|
||||
#define SE_RNG_IV_SIZE 16
|
||||
#define SE_RNG_DT_SIZE 16
|
||||
#define SE_RNG_KEY_SIZE 16
|
||||
#define SE_RNG_SEED_SIZE (SE_RNG_IV_SIZE + SE_RNG_KEY_SIZE + SE_RNG_DT_SIZE)
|
||||
|
||||
#define SE_AES_CMAC_DIGEST_SIZE 16
|
||||
#define SE_RSA512_DIGEST_SIZE 64
|
||||
#define SE_RSA1024_DIGEST_SIZE 128
|
||||
#define SE_RSA1536_DIGEST_SIZE 192
|
||||
#define SE_RSA2048_DIGEST_SIZE 256
|
||||
|
||||
/* SE register definitions */
|
||||
#define SE_SECURITY_0 0x000
|
||||
#define SE_KEY_SCHED_READ_SHIFT 3
|
||||
#define SE_SE_SECURITY_REG 0x000
|
||||
#define SE_HARD_SETTING BIT(0)
|
||||
#define SE_ENG_DIS BIT(1)
|
||||
#define SE_PERKEY_SETTING BIT(2)
|
||||
#define SE_SOFT_SETTING BIT(16)
|
||||
|
||||
#define SE_TZRAM_SECURITY_0 0x004
|
||||
#define SE_TZRAM_SECURITY_REG 0x004
|
||||
#define SE_TZRAM_HARD_SETTING BIT(0)
|
||||
#define SE_TZRAM_ENG_DIS BIT(1)
|
||||
|
||||
#define SE_CONFIG_REG_OFFSET 0x014
|
||||
#define SE_CONFIG_ENC_ALG_SHIFT 12
|
||||
#define SE_CONFIG_DEC_ALG_SHIFT 8
|
||||
#define ALG_AES_ENC 1
|
||||
#define ALG_RNG 2
|
||||
#define ALG_SHA 3
|
||||
#define ALG_RSA 4
|
||||
#define ALG_NOP 0
|
||||
#define ALG_AES_DEC 1
|
||||
#define SE_CONFIG_ENC_ALG(x) ((x) << SE_CONFIG_ENC_ALG_SHIFT)
|
||||
#define SE_CONFIG_DEC_ALG(x) ((x) << SE_CONFIG_DEC_ALG_SHIFT)
|
||||
#define SE_CONFIG_DST_SHIFT 2
|
||||
#define DST_MEMORY 0
|
||||
#define DST_HASHREG 1
|
||||
#define DST_KEYTAB 2
|
||||
#define DST_SRK 3
|
||||
#define DST_RSAREG 4
|
||||
#define SE_CONFIG_DST(x) ((x) << SE_CONFIG_DST_SHIFT)
|
||||
#define SE_CONFIG_ENC_MODE_SHIFT 24
|
||||
#define SE_CONFIG_DEC_MODE_SHIFT 16
|
||||
#define MODE_KEY128 0
|
||||
#define MODE_KEY192 1
|
||||
#define MODE_KEY256 2
|
||||
#define MODE_SHA1 0
|
||||
#define MODE_SHA224 4
|
||||
#define MODE_SHA256 5
|
||||
#define MODE_SHA384 6
|
||||
#define MODE_SHA512 7
|
||||
#define SE_CONFIG_ENC_MODE(x) ((x) << SE_CONFIG_ENC_MODE_SHIFT)
|
||||
#define SE_CONFIG_DEC_MODE(x) ((x) << SE_CONFIG_DEC_MODE_SHIFT)
|
||||
#define SE_OPERATION_REG 0x008
|
||||
#define SE_OP_ABORT 0
|
||||
#define SE_OP_START 1
|
||||
#define SE_OP_RESTART_OUT 2
|
||||
#define SE_OP_CTX_SAVE 3
|
||||
#define SE_OP_RESTART_IN 4
|
||||
|
||||
#define SE_RNG_CONFIG_REG_OFFSET 0x340
|
||||
#define RNG_MODE_SHIFT 0
|
||||
#define RNG_MODE_NORMAL 0
|
||||
#define RNG_MODE_FORCE_INSTANTION 1
|
||||
#define RNG_MODE_FORCE_RESEED 2
|
||||
#define SE_RNG_CONFIG_MODE(x) ((x) << RNG_MODE_SHIFT)
|
||||
#define RNG_SRC_SHIFT 2
|
||||
#define RNG_SRC_NONE 0
|
||||
#define RNG_SRC_ENTROPY 1
|
||||
#define RNG_SRC_LFSR 2
|
||||
#define SE_RNG_CONFIG_SRC(x) ((x) << RNG_SRC_SHIFT)
|
||||
#define SE_INT_ENABLE_REG 0x00C
|
||||
#define SE_INT_STATUS_REG 0x010
|
||||
#define SE_INT_IN_LL_BUF_RD BIT(0)
|
||||
#define SE_INT_IN_DONE BIT(1)
|
||||
#define SE_INT_OUT_LL_BUF_WR BIT(2)
|
||||
#define SE_INT_OUT_DONE BIT(3)
|
||||
#define SE_INT_OP_DONE BIT(4)
|
||||
#define SE_INT_RESEED_NEEDED BIT(5)
|
||||
#define SE_INT_ERR_STAT BIT(16)
|
||||
|
||||
#define SE_RNG_SRC_CONFIG_REG_OFFSET 0x344
|
||||
#define RNG_SRC_RO_ENT_SHIFT 1
|
||||
#define RNG_SRC_RO_ENT_ENABLE 1
|
||||
#define RNG_SRC_RO_ENT_DISABLE 0
|
||||
#define SE_RNG_SRC_CONFIG_ENT_SRC(x) ((x) << RNG_SRC_RO_ENT_SHIFT)
|
||||
#define RNG_SRC_RO_ENT_LOCK_SHIFT 0
|
||||
#define RNG_SRC_RO_ENT_LOCK_ENABLE 1
|
||||
#define RNG_SRC_RO_ENT_LOCK_DISABLE 0
|
||||
#define SE_RNG_SRC_CONFIG_ENT_SRC_LOCK(x) ((x) << RNG_SRC_RO_ENT_LOCK_SHIFT)
|
||||
#define SE_CONFIG_REG 0x014
|
||||
#define DST_MEMORY 0
|
||||
#define DST_HASHREG 1
|
||||
#define DST_KEYTABLE 2
|
||||
#define DST_SRK 3
|
||||
#define DST_RSAREG 4
|
||||
#define SE_CONFIG_DST(x) ((x) << 2)
|
||||
#define ALG_NOP 0
|
||||
#define ALG_AES_DEC 1
|
||||
#define SE_CONFIG_DEC_ALG(x) ((x) << 8)
|
||||
#define ALG_NOP 0
|
||||
#define ALG_AES_ENC 1
|
||||
#define ALG_RNG 2
|
||||
#define ALG_SHA 3
|
||||
#define ALG_RSA 4
|
||||
#define SE_CONFIG_ENC_ALG(x) ((x) << 12)
|
||||
#define MODE_KEY128 0
|
||||
#define MODE_KEY192 1
|
||||
#define MODE_KEY256 2
|
||||
#define MODE_SHA1 0
|
||||
#define MODE_SHA224 4
|
||||
#define MODE_SHA256 5
|
||||
#define MODE_SHA384 6
|
||||
#define MODE_SHA512 7
|
||||
#define SE_CONFIG_DEC_MODE(x) ((x) << 16)
|
||||
#define SE_CONFIG_ENC_MODE(x) ((x) << 24)
|
||||
|
||||
#define SE_RNG_RESEED_INTERVAL_REG_OFFSET 0x348
|
||||
#define SE_IN_LL_ADDR_REG 0x018
|
||||
#define SE_IN_CUR_BYTE_ADDR_REG 0x01C
|
||||
#define SE_IN_CUR_LL_ID_REG 0x020
|
||||
#define SE_OUT_LL_ADDR_REG 0x024
|
||||
#define SE_OUT_CUR_BYTE_ADDR_REG 0x028
|
||||
#define SE_OUT_CUR_LL_ID_REG 0x02C
|
||||
|
||||
#define SE_KEYTABLE_REG_OFFSET 0x31c
|
||||
#define SE_KEYTABLE_SLOT_SHIFT 4
|
||||
#define SE_KEYTABLE_SLOT(x) ((x) << SE_KEYTABLE_SLOT_SHIFT)
|
||||
#define SE_KEYTABLE_QUAD_SHIFT 2
|
||||
#define QUAD_KEYS_128 0
|
||||
#define QUAD_KEYS_192 1
|
||||
#define QUAD_KEYS_256 1
|
||||
#define QUAD_ORG_IV 2
|
||||
#define QUAD_UPDTD_IV 3
|
||||
#define SE_KEYTABLE_QUAD(x) ((x) << SE_KEYTABLE_QUAD_SHIFT)
|
||||
#define SE_KEYTABLE_OP_TYPE_SHIFT 9
|
||||
#define OP_READ 0
|
||||
#define OP_WRITE 1
|
||||
#define SE_KEYTABLE_OP_TYPE(x) ((x) << SE_KEYTABLE_OP_TYPE_SHIFT)
|
||||
#define SE_KEYTABLE_TABLE_SEL_SHIFT 8
|
||||
#define TABLE_KEYIV 0
|
||||
#define TABLE_SCHEDULE 1
|
||||
#define SE_KEYTABLE_TABLE_SEL(x) ((x) << SE_KEYTABLE_TABLE_SEL_SHIFT)
|
||||
#define SE_KEYTABLE_PKT_SHIFT 0
|
||||
#define SE_KEYTABLE_PKT(x) ((x) << SE_KEYTABLE_PKT_SHIFT)
|
||||
#define SE_HASH_RESULT_REG 0x030
|
||||
#define SE_HASH_RESULT_REG_COUNT 16
|
||||
|
||||
#define SE_OP_DONE_SHIFT 4
|
||||
#define OP_DONE 1
|
||||
#define SE_OP_DONE(x, y) ((x) && ((y) << SE_OP_DONE_SHIFT))
|
||||
#define SE_CONTEXT_SAVE_CONFIG_REG 0x070
|
||||
#define KEYS_0_3 0
|
||||
#define KEYS_4_7 1
|
||||
#define ORIGINAL_IV 2
|
||||
#define UPDATED_IV 3
|
||||
#define SE_CONTEXT_AES_WORD_QUAD(x) ((x) << 0)
|
||||
#define SE_CONTEXT_AES_KEY_INDEX(x) ((x) << 8)
|
||||
#define KEYS_0_3 0
|
||||
#define KEYS_4_7 1
|
||||
#define KEYS_8_11 2
|
||||
#define KEYS_12_15 3
|
||||
#define SE_CONTEXT_RSA_WORD_QUAD(x) ((x) << 12)
|
||||
#define SLOT0_EXPONENT 0
|
||||
#define SLOT0_MODULUS 1
|
||||
#define SLOT1_EXPONENT 2
|
||||
#define SLOT1_MODULUS 3
|
||||
#define SE_CONTEXT_RSA_KEY_INDEX(x) ((x) << 16)
|
||||
#define STICKY_0_3 0
|
||||
#define STICKY_4_7 1
|
||||
#define SE_CONTEXT_STICKY_WORD_QUAD(x) ((x) << 24)
|
||||
#define STICKY_BITS 0
|
||||
#define RSA_KEYTABLE 1
|
||||
#define AES_KEYTABLE 2
|
||||
#define MEM 4
|
||||
#define SRK 6
|
||||
#define SE_CONTEXT_SRC(x) ((x) << 29)
|
||||
|
||||
#define SE_CRYPTO_LAST_BLOCK 0x080
|
||||
#define SE_CTX_SAVE_AUTO_T210B01_REG 0x074
|
||||
#define SE_CTX_SAVE_AUTO_ENABLE BIT(0)
|
||||
#define SE_CTX_SAVE_AUTO_LOCK BIT(8)
|
||||
#define SE_CTX_SAVE_AUTO_CURR_CNT_MASK (0x3FF << 16)
|
||||
|
||||
#define SE_CRYPTO_REG_OFFSET 0x304
|
||||
#define SE_CRYPTO_HASH_SHIFT 0
|
||||
#define HASH_DISABLE 0
|
||||
#define HASH_ENABLE 1
|
||||
#define SE_CRYPTO_HASH(x) ((x) << SE_CRYPTO_HASH_SHIFT)
|
||||
#define SE_CRYPTO_XOR_POS_SHIFT 1
|
||||
#define XOR_BYPASS 0
|
||||
#define XOR_TOP 2
|
||||
#define XOR_BOTTOM 3
|
||||
#define SE_CRYPTO_XOR_POS(x) ((x) << SE_CRYPTO_XOR_POS_SHIFT)
|
||||
#define SE_CRYPTO_INPUT_SEL_SHIFT 3
|
||||
#define INPUT_AHB 0
|
||||
#define INPUT_RANDOM 1
|
||||
#define INPUT_AESOUT 2
|
||||
#define INPUT_LNR_CTR 3
|
||||
#define SE_CRYPTO_INPUT_SEL(x) ((x) << SE_CRYPTO_INPUT_SEL_SHIFT)
|
||||
#define SE_CRYPTO_VCTRAM_SEL_SHIFT 5
|
||||
#define VCTRAM_AHB 0
|
||||
#define VCTRAM_AESOUT 2
|
||||
#define VCTRAM_PREVAHB 3
|
||||
#define SE_CRYPTO_VCTRAM_SEL(x) ((x) << SE_CRYPTO_VCTRAM_SEL_SHIFT)
|
||||
#define SE_CRYPTO_IV_SEL_SHIFT 7
|
||||
#define IV_ORIGINAL 0
|
||||
#define IV_UPDATED 1
|
||||
#define SE_CRYPTO_IV_SEL(x) ((x) << SE_CRYPTO_IV_SEL_SHIFT)
|
||||
#define SE_CRYPTO_CORE_SEL_SHIFT 8
|
||||
#define CORE_DECRYPT 0
|
||||
#define CORE_ENCRYPT 1
|
||||
#define SE_CRYPTO_CORE_SEL(x) ((x) << SE_CRYPTO_CORE_SEL_SHIFT)
|
||||
#define SE_CRYPTO_CTR_VAL_SHIFT 11
|
||||
#define SE_CRYPTO_CTR_VAL(x) ((x) << SE_CRYPTO_CTR_VAL_SHIFT)
|
||||
#define SE_CRYPTO_KEY_INDEX_SHIFT 24
|
||||
#define SE_CRYPTO_KEY_INDEX(x) ((x) << SE_CRYPTO_KEY_INDEX_SHIFT)
|
||||
#define SE_CRYPTO_CTR_CNTN_SHIFT 11
|
||||
#define SE_CRYPTO_CTR_CNTN(x) ((x) << SE_CRYPTO_CTR_CNTN_SHIFT)
|
||||
#define SE_CRYPTO_LAST_BLOCK 0x080
|
||||
|
||||
#define SE_CRYPTO_CTR_REG_COUNT 4
|
||||
#define SE_CRYPTO_CTR_REG_OFFSET 0x308
|
||||
|
||||
#define SE_OPERATION_REG_OFFSET 0x008
|
||||
#define SE_OPERATION_SHIFT 0
|
||||
#define OP_ABORT 0
|
||||
#define OP_START 1
|
||||
#define OP_RESTART 2
|
||||
#define OP_CTX_SAVE 3
|
||||
#define OP_RESTART_IN 4
|
||||
#define SE_OPERATION(x) ((x) << SE_OPERATION_SHIFT)
|
||||
|
||||
#define SE_CONTEXT_SAVE_CONFIG_REG_OFFSET 0x070
|
||||
#define SE_CONTEXT_SAVE_WORD_QUAD_SHIFT 0
|
||||
#define KEYS_0_3 0
|
||||
#define KEYS_4_7 1
|
||||
#define ORIG_IV 2
|
||||
#define UPD_IV 3
|
||||
#define SE_CONTEXT_SAVE_WORD_QUAD(x) ((x) << SE_CONTEXT_SAVE_WORD_QUAD_SHIFT)
|
||||
|
||||
#define SE_CONTEXT_SAVE_KEY_INDEX_SHIFT 8
|
||||
#define SE_CONTEXT_SAVE_KEY_INDEX(x) ((x) << SE_CONTEXT_SAVE_KEY_INDEX_SHIFT)
|
||||
|
||||
#define SE_CONTEXT_SAVE_STICKY_WORD_QUAD_SHIFT 24
|
||||
#define STICKY_0_3 0
|
||||
#define STICKY_4_7 1
|
||||
#define SE_CONTEXT_SAVE_STICKY_WORD_QUAD(x) \
|
||||
((x) << SE_CONTEXT_SAVE_STICKY_WORD_QUAD_SHIFT)
|
||||
|
||||
#define SE_CONTEXT_SAVE_SRC_SHIFT 29
|
||||
#define STICKY_BITS 0
|
||||
#define KEYTABLE 2
|
||||
#define MEM 4
|
||||
#define SRK 6
|
||||
|
||||
#define RSA_KEYTABLE 1
|
||||
#define AES_KEYTABLE 2
|
||||
#define SE_CONTEXT_SAVE_SRC(x) ((x) << SE_CONTEXT_SAVE_SRC_SHIFT)
|
||||
|
||||
#define SE_CONTEXT_SAVE_RSA_KEY_INDEX_SHIFT 16
|
||||
#define SE_CONTEXT_SAVE_RSA_KEY_INDEX(x) \
|
||||
((x) << SE_CONTEXT_SAVE_RSA_KEY_INDEX_SHIFT)
|
||||
|
||||
#define SE_CONTEXT_RSA_WORD_QUAD_SHIFT 12
|
||||
#define SE_CONTEXT_RSA_WORD_QUAD(x) \
|
||||
((x) << SE_CONTEXT_RSA_WORD_QUAD_SHIFT)
|
||||
|
||||
#define SE_CTX_SAVE_AUTO 0x074
|
||||
#define CTX_SAVE_AUTO_ENABLE BIT(0)
|
||||
#define CTX_SAVE_AUTO_LOCK BIT(8)
|
||||
#define CTX_SAVE_AUTO_CURR_CNT_MASK (0x3FF << 16)
|
||||
|
||||
#define SE_INT_ENABLE_REG_OFFSET 0x00c
|
||||
#define SE_INT_STATUS_REG_OFFSET 0x010
|
||||
#define INT_DISABLE 0
|
||||
#define INT_ENABLE 1
|
||||
#define INT_UNSET 0
|
||||
#define INT_SET 1
|
||||
#define SE_INT_OP_DONE_SHIFT 4
|
||||
#define SE_INT_OP_DONE(x) ((x) << SE_INT_OP_DONE_SHIFT)
|
||||
#define SE_INT_ERROR_SHIFT 16
|
||||
#define SE_INT_ERROR(x) ((x) << SE_INT_ERROR_SHIFT)
|
||||
|
||||
#define SE_STATUS_0 0x800
|
||||
#define SE_STATUS_0_STATE_WAIT_IN 3
|
||||
|
||||
#define SE_ERR_STATUS_0 0x804
|
||||
#define SE_ERR_STATUS_0_SE_NS_ACCESS_CLEAR 0
|
||||
|
||||
#define SE_CRYPTO_KEYTABLE_DST_REG_OFFSET 0X330
|
||||
#define SE_CRYPTO_KEYTABLE_DST_WORD_QUAD_SHIFT 0
|
||||
#define SE_CRYPTO_KEYTABLE_DST_WORD_QUAD(x) \
|
||||
((x) << SE_CRYPTO_KEYTABLE_DST_WORD_QUAD_SHIFT)
|
||||
|
||||
#define SE_KEY_INDEX_SHIFT 8
|
||||
#define SE_CRYPTO_KEYTABLE_DST_KEY_INDEX(x) ((x) << SE_KEY_INDEX_SHIFT)
|
||||
|
||||
#define SE_IN_LL_ADDR_REG_OFFSET 0x018
|
||||
#define SE_OUT_LL_ADDR_REG_OFFSET 0x024
|
||||
|
||||
#define SE_KEYTABLE_DATA0_REG_OFFSET 0x320
|
||||
#define SE_KEYTABLE_REG_MAX_DATA 16
|
||||
|
||||
#define SE_BLOCK_COUNT_REG_OFFSET 0x318
|
||||
|
||||
#define SE_SPARE_0_REG_OFFSET 0x80c
|
||||
|
||||
#define SE_SHA_CONFIG_REG_OFFSET 0x200
|
||||
#define SE_SHA_CONFIG_REG 0x200
|
||||
#define SHA_CONTINUE 0
|
||||
#define SHA_INIT_HASH 1
|
||||
|
||||
#define SE_SHA_MSG_LENGTH_0_REG_OFFSET 0x204
|
||||
#define SE_SHA_MSG_LENGTH_1_REG_OFFSET 0x208
|
||||
#define SE_SHA_MSG_LENGTH_2_REG_OFFSET 0x20C
|
||||
#define SE_SHA_MSG_LENGTH_3_REG_OFFSET 0x210
|
||||
#define SE_SHA_MSG_LEFT_0_REG_OFFSET 0x214
|
||||
#define SE_SHA_MSG_LEFT_1_REG_OFFSET 0x218
|
||||
#define SE_SHA_MSG_LEFT_2_REG_OFFSET 0x21C
|
||||
#define SE_SHA_MSG_LEFT_3_REG_OFFSET 0x220
|
||||
#define SE_SHA_MSG_LENGTH_0_REG 0x204
|
||||
#define SE_SHA_MSG_LENGTH_1_REG 0x208
|
||||
#define SE_SHA_MSG_LENGTH_2_REG 0x20C
|
||||
#define SE_SHA_MSG_LENGTH_3_REG 0x210
|
||||
#define SE_SHA_MSG_LEFT_0_REG 0x214
|
||||
#define SE_SHA_MSG_LEFT_1_REG 0x218
|
||||
#define SE_SHA_MSG_LEFT_2_REG 0x21C
|
||||
#define SE_SHA_MSG_LEFT_3_REG 0x220
|
||||
|
||||
#define SE_HASH_RESULT_REG_COUNT 16
|
||||
#define SE_HASH_RESULT_REG_OFFSET 0x030
|
||||
#define TEGRA_SE_KEY_256_SIZE 32
|
||||
#define TEGRA_SE_KEY_192_SIZE 24
|
||||
#define TEGRA_SE_KEY_128_SIZE 16
|
||||
#define TEGRA_SE_AES_BLOCK_SIZE 16
|
||||
#define TEGRA_SE_AES_MIN_KEY_SIZE 16
|
||||
#define TEGRA_SE_AES_MAX_KEY_SIZE 32
|
||||
#define TEGRA_SE_AES_IV_SIZE 16
|
||||
#define TEGRA_SE_SHA_512_SIZE 64
|
||||
#define TEGRA_SE_SHA_384_SIZE 48
|
||||
#define TEGRA_SE_SHA_256_SIZE 32
|
||||
#define TEGRA_SE_SHA_192_SIZE 24
|
||||
#define TEGRA_SE_RNG_IV_SIZE 16
|
||||
#define TEGRA_SE_RNG_DT_SIZE 16
|
||||
#define TEGRA_SE_RNG_KEY_SIZE 16
|
||||
#define TEGRA_SE_RNG_SEED_SIZE (TEGRA_SE_RNG_IV_SIZE + \
|
||||
TEGRA_SE_RNG_KEY_SIZE + \
|
||||
TEGRA_SE_RNG_DT_SIZE)
|
||||
#define SE_CRYPTO_SECURITY_PERKEY_REG 0x280
|
||||
#define SE_KEY_LOCK_FLAG 0x80
|
||||
#define SE_CRYPTO_KEYTABLE_ACCESS_REG 0x284
|
||||
#define SE_CRYPTO_KEYTABLE_ACCESS_REG_COUNT 16
|
||||
#define SE_KEY_TBL_DIS_KEYREAD_FLAG BIT(0)
|
||||
#define SE_KEY_TBL_DIS_KEYUPDATE_FLAG BIT(1)
|
||||
#define SE_KEY_TBL_DIS_OIVREAD_FLAG BIT(2)
|
||||
#define SE_KEY_TBL_DIS_OIVUPDATE_FLAG BIT(3)
|
||||
#define SE_KEY_TBL_DIS_UIVREAD_FLAG BIT(4)
|
||||
#define SE_KEY_TBL_DIS_UIVUPDATE_FLAG BIT(5)
|
||||
#define SE_KEY_TBL_DIS_KEYUSE_FLAG BIT(6)
|
||||
#define SE_KEY_TBL_DIS_KEY_ACCESS_FLAG 0x7F
|
||||
|
||||
#define TEGRA_SE_AES_CMAC_DIGEST_SIZE 16
|
||||
#define TEGRA_SE_RSA512_DIGEST_SIZE 64
|
||||
#define TEGRA_SE_RSA1024_DIGEST_SIZE 128
|
||||
#define TEGRA_SE_RSA1536_DIGEST_SIZE 192
|
||||
#define TEGRA_SE_RSA2048_DIGEST_SIZE 256
|
||||
#define SE_CRYPTO_CONFIG_REG 0x304
|
||||
#define HASH_DISABLE 0
|
||||
#define HASH_ENABLE 1
|
||||
#define SE_CRYPTO_HASH(x) ((x) << 0)
|
||||
#define XOR_BYPASS 0
|
||||
#define XOR_TOP 2
|
||||
#define XOR_BOTTOM 3
|
||||
#define SE_CRYPTO_XOR_POS(x) ((x) << 1)
|
||||
#define INPUT_MEMORY 0
|
||||
#define INPUT_RANDOM 1
|
||||
#define INPUT_AESOUT 2
|
||||
#define INPUT_LNR_CTR 3
|
||||
#define SE_CRYPTO_INPUT_SEL(x) ((x) << 3)
|
||||
#define VCTRAM_MEM 0
|
||||
#define VCTRAM_AESOUT 2
|
||||
#define VCTRAM_PREVMEM 3
|
||||
#define SE_CRYPTO_VCTRAM_SEL(x) ((x) << 5)
|
||||
#define IV_ORIGINAL 0
|
||||
#define IV_UPDATED 1
|
||||
#define SE_CRYPTO_IV_SEL(x) ((x) << 7)
|
||||
#define CORE_DECRYPT 0
|
||||
#define CORE_ENCRYPT 1
|
||||
#define SE_CRYPTO_CORE_SEL(x) ((x) << 8)
|
||||
#define SE_CRYPTO_KEYSCH_BYPASS BIT(10)
|
||||
#define SE_CRYPTO_CTR_CNTN(x) ((x) << 11)
|
||||
#define SE_CRYPTO_KEY_INDEX(x) ((x) << 24)
|
||||
#define MEMIF_AHB 0
|
||||
#define MEMIF_MCCIF 1
|
||||
#define SE_CRYPTO_MEMIF(x) ((x) << 31)
|
||||
|
||||
#define SE_KEY_TABLE_ACCESS_LOCK_OFFSET 0x280
|
||||
#define SE_KEY_TBL_DIS_KEY_LOCK_FLAG 0x80
|
||||
#define SE_CRYPTO_LINEAR_CTR_REG 0x308
|
||||
#define SE_CRYPTO_LINEAR_CTR_REG_COUNT 4
|
||||
|
||||
#define SE_KEY_TABLE_ACCESS_REG_OFFSET 0x284
|
||||
#define SE_KEY_TBL_DIS_KEYREAD_FLAG BIT(0)
|
||||
#define SE_KEY_TBL_DIS_KEYUPDATE_FLAG BIT(1)
|
||||
#define SE_KEY_TBL_DIS_OIVREAD_FLAG BIT(2)
|
||||
#define SE_KEY_TBL_DIS_OIVUPDATE_FLAG BIT(3)
|
||||
#define SE_KEY_TBL_DIS_UIVREAD_FLAG BIT(4)
|
||||
#define SE_KEY_TBL_DIS_UIVUPDATE_FLAG BIT(5)
|
||||
#define SE_KEY_TBL_DIS_KEYUSE_FLAG BIT(6)
|
||||
#define SE_KEY_TBL_DIS_KEY_ACCESS_FLAG 0x7F
|
||||
#define SE_CRYPTO_BLOCK_COUNT_REG 0x318
|
||||
|
||||
#define SE_KEY_READ_DISABLE_SHIFT 0
|
||||
#define SE_KEY_UPDATE_DISABLE_SHIFT 1
|
||||
#define SE_CRYPTO_KEYTABLE_ADDR_REG 0x31C
|
||||
#define SE_KEYTABLE_PKT(x) ((x) << 0)
|
||||
#define KEYS_0_3 0
|
||||
#define KEYS_4_7 1
|
||||
#define ORIGINAL_IV 2
|
||||
#define UPDATED_IV 3
|
||||
#define SE_KEYTABLE_QUAD(x) ((x) << 2)
|
||||
#define SE_KEYTABLE_SLOT(x) ((x) << 4)
|
||||
|
||||
#define SE_CONTEXT_BUFER_SIZE 1072
|
||||
#define SE_CONTEXT_DRBG_BUFER_SIZE 2112
|
||||
#define SE_CRYPTO_KEYTABLE_DATA_REG 0x320
|
||||
|
||||
#define SE_CONTEXT_SAVE_RANDOM_DATA_OFFSET 0
|
||||
#define SE_CONTEXT_SAVE_RANDOM_DATA_SIZE 16
|
||||
#define SE_CONTEXT_SAVE_STICKY_BITS_OFFSET \
|
||||
(SE_CONTEXT_SAVE_RANDOM_DATA_OFFSET + SE_CONTEXT_SAVE_RANDOM_DATA_SIZE)
|
||||
#define SE_CONTEXT_SAVE_STICKY_BITS_SIZE 16
|
||||
#define SE_CRYPTO_KEYTABLE_DST_REG 0x330
|
||||
#define KEYS_0_3 0
|
||||
#define KEYS_4_7 1
|
||||
#define ORIGINAL_IV 2
|
||||
#define UPDATED_IV 3
|
||||
#define SE_KEYTABLE_DST_WORD_QUAD(x) ((x) << 0)
|
||||
#define SE_KEYTABLE_DST_KEY_INDEX(x) ((x) << 8)
|
||||
|
||||
#define SE_CONTEXT_SAVE_KEYS_OFFSET (SE_CONTEXT_SAVE_STICKY_BITS_OFFSET + \
|
||||
SE_CONTEXT_SAVE_STICKY_BITS_SIZE)
|
||||
#define SE11_CONTEXT_SAVE_KEYS_OFFSET (SE_CONTEXT_SAVE_STICKY_BITS_OFFSET + \
|
||||
SE_CONTEXT_SAVE_STICKY_BITS_SIZE + \
|
||||
SE_CONTEXT_SAVE_STICKY_BITS_SIZE)
|
||||
#define SE_RNG_CONFIG_REG 0x340
|
||||
#define MODE_NORMAL 0
|
||||
#define MODE_FORCE_INSTANTION 1
|
||||
#define MODE_FORCE_RESEED 2
|
||||
#define SE_RNG_CONFIG_MODE(x) ((x) << 0)
|
||||
#define SRC_NONE 0
|
||||
#define SRC_ENTROPY 1
|
||||
#define SRC_LFSR 2
|
||||
#define SE_RNG_CONFIG_SRC(x) ((x) << 2)
|
||||
|
||||
#define SE_CONTEXT_SAVE_KEY_LENGTH 512
|
||||
#define SE_CONTEXT_ORIGINAL_IV_OFFSET (SE_CONTEXT_SAVE_KEYS_OFFSET + \
|
||||
SE_CONTEXT_SAVE_KEY_LENGTH)
|
||||
#define SE11_CONTEXT_ORIGINAL_IV_OFFSET (SE11_CONTEXT_SAVE_KEYS_OFFSET + \
|
||||
SE_CONTEXT_SAVE_KEY_LENGTH)
|
||||
#define SE_RNG_SRC_CONFIG_REG 0x344
|
||||
#define RO_ENTR_LOCK_DISABLE 0
|
||||
#define RO_ENTR_LOCK_ENABLE 1
|
||||
#define SE_RNG_SRC_CONFIG_ENTR_SRC_LOCK(x) ((x) << 0)
|
||||
#define RO_ENTR_DISABLE 0
|
||||
#define RO_ENTR_ENABLE 1
|
||||
#define SE_RNG_SRC_CONFIG_ENTR_SRC(x) ((x) << 1)
|
||||
#define RO_HW_DIS_CYA_DISABLE 0
|
||||
#define RO_HW_DIS_CYA_ENABLE 1
|
||||
#define SE_RNG_SRC_CONFIG_HW_DIS_CYA(x) ((x) << 2)
|
||||
#define SE_RNG_SRC_CONFIG_ENTR_SUBSMPL(x) ((x) << 4)
|
||||
#define SE_RNG_SRC_CONFIG_ENTR_DATA_FLUSH BIT(8)
|
||||
|
||||
#define SE_CONTEXT_ORIGINAL_IV_LENGTH 256
|
||||
#define SE_RNG_RESEED_INTERVAL_REG 0x348
|
||||
|
||||
#define SE_CONTEXT_UPDATED_IV_OFFSET (SE_CONTEXT_ORIGINAL_IV_OFFSET + \
|
||||
SE_CONTEXT_ORIGINAL_IV_LENGTH)
|
||||
#define SE11_CONTEXT_UPDATED_IV_OFFSET (SE11_CONTEXT_ORIGINAL_IV_OFFSET + \
|
||||
SE_CONTEXT_ORIGINAL_IV_LENGTH)
|
||||
#define SE_RSA_CONFIG 0x400
|
||||
#define RSA_KEY_SLOT_ONE 0
|
||||
#define RSA_KEY_SLOT_TW0 1
|
||||
#define RSA_KEY_SLOT(x) ((x) << 24)
|
||||
|
||||
#define SE_CONTEXT_UPDATED_IV_LENGTH 256
|
||||
#define SE_RSA_KEY_SIZE_REG 0x404
|
||||
#define RSA_KEY_WIDTH_512 0
|
||||
#define RSA_KEY_WIDTH_1024 1
|
||||
#define RSA_KEY_WIDTH_1536 2
|
||||
#define RSA_KEY_WIDTH_2048 3
|
||||
|
||||
#define SE_CONTEXT_SAVE_KNOWN_PATTERN_OFFSET (SE_CONTEXT_UPDATED_IV_OFFSET + \
|
||||
SE_CONTEXT_UPDATED_IV_LENGTH)
|
||||
#define SE11_CONTEXT_SAVE_KNOWN_PATTERN_OFFSET \
|
||||
(SE11_CONTEXT_UPDATED_IV_OFFSET + \
|
||||
SE_CONTEXT_UPDATED_IV_LENGTH)
|
||||
#define SE_RSA_EXP_SIZE_REG 0x408
|
||||
|
||||
#define SE_CONTEXT_SAVE_RSA_KEYS_OFFSET SE11_CONTEXT_SAVE_KNOWN_PATTERN_OFFSET
|
||||
#define SE_RSA_SECURITY_PERKEY_REG 0x40C
|
||||
#define SE_RSA_KEY_LOCK_FLAG 0x80
|
||||
#define SE_RSA_KEYTABLE_ACCESS_REG 0x410
|
||||
#define SE_RSA_KEY_TBL_DIS_KEYREAD_FLAG BIT(0)
|
||||
#define SE_RSA_KEY_TBL_DIS_KEYUPDATE_FLAG BIT(1)
|
||||
#define SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG BIT(2)
|
||||
#define SE_RSA_KEY_TBL_DIS_KEY_ACCESS_FLAG 0x7F
|
||||
#define SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_FLAG (SE_RSA_KEY_TBL_DIS_KEYREAD_FLAG | SE_RSA_KEY_TBL_DIS_KEYUPDATE_FLAG)
|
||||
#define SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_USE_FLAG (SE_RSA_KEY_TBL_DIS_KEYREAD_FLAG | SE_RSA_KEY_TBL_DIS_KEYUPDATE_FLAG | SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG)
|
||||
|
||||
#define SE_CONTEXT_SAVE_RSA_KEY_LENGTH 1024
|
||||
#define SE_RSA_KEYTABLE_ADDR_REG 0x420
|
||||
#define SE_RSA_KEYTABLE_PKT(x) ((x) << 0)
|
||||
#define RSA_KEY_TYPE_EXP 0
|
||||
#define RSA_KEY_TYPE_MOD 1
|
||||
#define SE_RSA_KEYTABLE_TYPE(x) ((x) << 6)
|
||||
#define RSA_KEY_NUM(x) ((x) << 7)
|
||||
#define RSA_KEY_INPUT_MODE_REG 0
|
||||
#define RSA_KEY_INPUT_MODE_DMA 1
|
||||
#define SE_RSA_KEYTABLE_INPUT_MODE(x) ((x) << 8)
|
||||
#define RSA_KEY_READ 0
|
||||
#define RSA_KEY_WRITE 1
|
||||
#define SE_RSA_KEY_OP(x) ((x) << 10)
|
||||
|
||||
#define SE_CONTEXT_SAVE_RSA_KNOWN_PATTERN_OFFSET \
|
||||
(SE_CONTEXT_SAVE_RSA_KEYS_OFFSET + SE_CONTEXT_SAVE_RSA_KEY_LENGTH)
|
||||
#define SE_RSA_KEYTABLE_DATA_REG 0x424
|
||||
|
||||
#define SE_CONTEXT_KNOWN_PATTERN_SIZE 16
|
||||
#define SE_RSA_OUTPUT_REG 0x428
|
||||
#define SE_RSA_OUTPUT_REG_COUNT 64
|
||||
|
||||
#define TEGRA_SE_RSA_KEYSLOT_COUNT 2
|
||||
#define SE_STATUS_REG 0x800
|
||||
#define SE_STATUS_STATE_IDLE 0
|
||||
#define SE_STATUS_STATE_BUSY 1
|
||||
#define SE_STATUS_STATE_WAIT_OUT 2
|
||||
#define SE_STATUS_STATE_WAIT_IN 3
|
||||
#define SE_STATUS_STATE_MASK 3
|
||||
|
||||
#define SE_RSA_KEYTABLE_ACCESS_LOCK_OFFSET 0x40C
|
||||
#define SE_RSA_KEY_TBL_DIS_KEY_LOCK_FLAG 0x80
|
||||
#define SE_ERR_STATUS_REG 0x804
|
||||
#define SE_ERR_STATUS_SE_NS_ACCESS BIT(0)
|
||||
#define SE_ERR_STATUS_BUSY_REG_WR BIT(1)
|
||||
#define SE_ERR_STATUS_DST BIT(2)
|
||||
#define SE_ERR_STATUS_SRK_USAGE_LIMIT BIT(3)
|
||||
#define SE_ERR_STATUS_TZRAM_NS_ACCESS BIT(24)
|
||||
#define SE_ERR_STATUS_TZRAM_ADDRESS BIT(25)
|
||||
|
||||
#define SE_RSA_KEYTABLE_ACCESS_REG_OFFSET 0x410
|
||||
#define SE_RSA_KEY_TBL_DIS_KEYREAD_FLAG BIT(0)
|
||||
#define SE_RSA_KEY_TBL_DIS_KEYUPDATE_FLAG BIT(1)
|
||||
#define SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_FLAG (SE_RSA_KEY_TBL_DIS_KEYREAD_FLAG | SE_RSA_KEY_TBL_DIS_KEYUPDATE_FLAG)
|
||||
#define SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG BIT(2)
|
||||
#define SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG_SHIFT BIT(2)
|
||||
#define SE_RSA_KEY_TBL_DIS_KEY_ALL_COMMON_FLAG 7
|
||||
#define SE_RSA_KEY_TBL_DIS_KEY_ALL_FLAG 0x7F
|
||||
#define SE_MISC_REG 0x808
|
||||
#define SE_ENTROPY_NEXT_192BIT BIT(0)
|
||||
#define SE_ENTROPY_VN_BYPASS BIT(1)
|
||||
#define SE_CLK_OVR_ON BIT(2)
|
||||
|
||||
#define SE_RSA_KEYTABLE_ADDR 0x420
|
||||
#define SE_RSA_KEYTABLE_DATA 0x424
|
||||
#define SE_RSA_OUTPUT 0x428
|
||||
#define SE_SPARE_REG 0x80C
|
||||
#define SE_ERRATA_FIX_DISABLE 0
|
||||
#define SE_ERRATA_FIX_ENABLE 1
|
||||
#define SE_ECO(x) ((x) << 0)
|
||||
|
||||
#define RSA_KEY_READ 0
|
||||
#define RSA_KEY_WRITE 1
|
||||
#define SE_RSA_KEY_OP_SHIFT 10
|
||||
#define SE_RSA_KEY_OP(x) ((x) << SE_RSA_KEY_OP_SHIFT)
|
||||
|
||||
#define RSA_KEY_INPUT_MODE_REG 0
|
||||
#define RSA_KEY_INPUT_MODE_DMA 1
|
||||
#define RSA_KEY_INPUT_MODE_SHIFT 8
|
||||
#define RSA_KEY_INPUT_MODE(x) ((x) << RSA_KEY_INPUT_MODE_SHIFT)
|
||||
|
||||
#define RSA_KEY_SLOT_ONE 0
|
||||
#define RSA_KEY_SLOT_TW0 1
|
||||
#define RSA_KEY_NUM_SHIFT 7
|
||||
#define RSA_KEY_NUM(x) ((x) << RSA_KEY_NUM_SHIFT)
|
||||
|
||||
#define RSA_KEY_TYPE_EXP 0
|
||||
#define RSA_KEY_TYPE_MOD 1
|
||||
#define RSA_KEY_TYPE_SHIFT 6
|
||||
#define RSA_KEY_TYPE(x) ((x) << RSA_KEY_TYPE_SHIFT)
|
||||
|
||||
#define SE_RSA_KEY_SIZE_REG_OFFSET 0x404
|
||||
#define SE_RSA_EXP_SIZE_REG_OFFSET 0x408
|
||||
|
||||
#define RSA_KEY_SLOT_SHIFT 24
|
||||
#define RSA_KEY_SLOT(x) ((x) << RSA_KEY_SLOT_SHIFT)
|
||||
#define SE_RSA_CONFIG 0x400
|
||||
|
||||
#define RSA_KEY_PKT_WORD_ADDR_SHIFT 0
|
||||
#define RSA_KEY_PKT_WORD_ADDR(x) ((x) << RSA_KEY_PKT_WORD_ADDR_SHIFT)
|
||||
|
||||
#define RSA_KEY_WORD_ADDR_SHIFT 0
|
||||
#define RSA_KEY_WORD_ADDR(x) ((x) << RSA_KEY_WORD_ADDR_SHIFT)
|
||||
|
||||
#define SE_RSA_KEYTABLE_PKT_SHIFT 0
|
||||
#define SE_RSA_KEYTABLE_PKT(x) ((x) << SE_RSA_KEYTABLE_PKT_SHIFT)
|
||||
|
||||
#endif /* _CRYPTO_TEGRA_SE_H */
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2018-2019 CTCaer
|
||||
* Copyright (c) 2018-2021 CTCaer
|
||||
* Copyright (c) 2018 balika011
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
|
|
@ -70,7 +70,7 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
|
|||
u32 *pkg11_magic_off;
|
||||
|
||||
bpmp_mmu_disable();
|
||||
bpmp_clk_rate_set(BPMP_CLK_NORMAL);
|
||||
bpmp_freq_t prev_fid = bpmp_clk_rate_set(BPMP_CLK_NORMAL);
|
||||
|
||||
// Enable clocks.
|
||||
clock_enable_host1x();
|
||||
|
|
@ -190,7 +190,7 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
|
|||
if (kb == KB_TSEC_FW_EMU_COMPAT)
|
||||
{
|
||||
u32 start = get_tmr_us();
|
||||
u32 k = se[SE_KEYTABLE_DATA0_REG_OFFSET / 4];
|
||||
u32 k = se[SE_CRYPTO_KEYTABLE_DATA_REG / 4];
|
||||
u32 key[16] = {0};
|
||||
u32 kidx = 0;
|
||||
|
||||
|
|
@ -198,9 +198,9 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
|
|||
{
|
||||
smmu_flush_all();
|
||||
|
||||
if (k != se[SE_KEYTABLE_DATA0_REG_OFFSET / 4])
|
||||
if (k != se[SE_CRYPTO_KEYTABLE_DATA_REG / 4])
|
||||
{
|
||||
k = se[SE_KEYTABLE_DATA0_REG_OFFSET / 4];
|
||||
k = se[SE_CRYPTO_KEYTABLE_DATA_REG / 4];
|
||||
key[kidx++] = k;
|
||||
}
|
||||
|
||||
|
|
@ -269,7 +269,7 @@ int tsec_query(u8 *tsec_keys, u8 kb, tsec_ctxt_t *tsec_ctxt)
|
|||
SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB) = 0;
|
||||
SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB) = 0;
|
||||
|
||||
memcpy(tsec_keys, &buf, 0x10);
|
||||
memcpy(tsec_keys, &buf, SE_KEY_128_SIZE);
|
||||
}
|
||||
|
||||
out_free:;
|
||||
|
|
@ -284,7 +284,7 @@ out:;
|
|||
clock_disable_sor_safe();
|
||||
clock_disable_tsec();
|
||||
bpmp_mmu_enable();
|
||||
bpmp_clk_rate_set(BPMP_CLK_DEFAULT_BOOST);
|
||||
bpmp_clk_rate_set(prev_fid);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue