You aint taking this down
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Slluxx
parent
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398 changed files with 116325 additions and 35 deletions
99
bdk/power/bm92t36.c
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99
bdk/power/bm92t36.c
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/*
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* USB-PD driver for Nintendo Switch's TI BM92T36
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*
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* Copyright (c) 2020 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <string.h>
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#include "bm92t36.h"
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#include <soc/i2c.h>
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#include <utils/util.h>
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#define ALERT_STATUS_REG 0x2
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#define STATUS1_REG 0x3
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#define STATUS2_REG 0x4
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#define COMMAND_REG 0x5
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#define CONFIG1_REG 0x6
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#define DEV_CAPS_REG 0x7
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#define READ_PDOS_SRC_REG 0x8
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#define CONFIG2_REG 0x17
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#define DP_STATUS_REG 0x18
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#define DP_ALERT_EN_REG 0x19
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#define VENDOR_CONFIG_REG 0x1A
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#define AUTO_NGT_FIXED_REG 0x20
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#define AUTO_NGT_BATT_REG 0x23
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#define SYS_CONFIG1_REG 0x26
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#define SYS_CONFIG2_REG 0x27
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#define CURRENT_PDO_REG 0x28
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#define CURRENT_RDO_REG 0x2B
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#define ALERT_ENABLE_REG 0x2E
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#define SYS_CONFIG3_REG 0x2F
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#define SET_RDO_REG 0x30
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#define PDOS_SNK_REG 0x33
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#define PDOS_SRC_PROV_REG 0x3C
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#define FW_TYPE_REG 0x4B
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#define FW_REVISION_REG 0x4C
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#define MAN_ID_REG 0x4D
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#define DEV_ID_REG 0x4E
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#define REV_ID_REG 0x4F
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#define INCOMING_VDM_REG 0x50
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#define OUTGOING_VDM_REG 0x60
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#define STATUS1_INSERT BIT(7) // Cable inserted.
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typedef struct _pd_object_t {
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unsigned int amp:10;
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unsigned int volt:10;
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unsigned int info:10;
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unsigned int type:2;
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} __attribute__((packed)) pd_object_t;
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static int _bm92t36_read_reg(u8 *buf, u32 size, u32 reg)
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{
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return i2c_recv_buf_big(buf, size, I2C_1, BM92T36_I2C_ADDR, reg);
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}
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void bm92t36_get_sink_info(bool *inserted, usb_pd_objects_t *usb_pd)
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{
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u8 buf[32];
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pd_object_t pdos[7];
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if (inserted)
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{
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_bm92t36_read_reg(buf, 2, STATUS1_REG);
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*inserted = buf[0] & STATUS1_INSERT ? true : false;
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}
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if (usb_pd)
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{
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_bm92t36_read_reg(buf, 29, READ_PDOS_SRC_REG);
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memcpy(pdos, &buf[1], 28);
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memset(usb_pd, 0, sizeof(usb_pd_objects_t));
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usb_pd->pdo_no = buf[0] / sizeof(pd_object_t);
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for (u32 i = 0; i < usb_pd->pdo_no; i++)
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{
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usb_pd->pdos[i].amperage = pdos[i].amp * 10;
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usb_pd->pdos[i].voltage = (pdos[i].volt * 50) / 1000;
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}
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_bm92t36_read_reg(buf, 5, CURRENT_PDO_REG);
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memcpy(pdos, &buf[1], 4);
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usb_pd->selected_pdo.amperage = pdos[0].amp * 10;
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usb_pd->selected_pdo.voltage = (pdos[0].volt * 50) / 1000;
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}
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}
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41
bdk/power/bm92t36.h
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41
bdk/power/bm92t36.h
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/*
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* USB-PD driver for Nintendo Switch's TI BM92T36
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*
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* Copyright (c) 2020 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __BM92T36_H_
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#define __BM92T36_H_
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#include <utils/types.h>
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#define BM92T36_I2C_ADDR 0x18
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typedef struct _usb_pd_object_t
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{
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u32 amperage;
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u32 voltage;
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} usb_pd_object_t;
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typedef struct _usb_pd_objects_t
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{
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u32 pdo_no;
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usb_pd_object_t pdos[7];
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usb_pd_object_t selected_pdo;
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} usb_pd_objects_t;
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void bm92t36_get_sink_info(bool *inserted, usb_pd_objects_t *usb_pd);
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#endif
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178
bdk/power/bq24193.c
Normal file
178
bdk/power/bq24193.c
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@ -0,0 +1,178 @@
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/*
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* Battery charger driver for Nintendo Switch's TI BQ24193
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*
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* Copyright (c) 2018 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "bq24193.h"
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#include <soc/i2c.h>
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#include <utils/util.h>
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static u8 bq24193_get_reg(u8 reg)
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{
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return i2c_recv_byte(I2C_1, BQ24193_I2C_ADDR, reg);
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}
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int bq24193_get_property(enum BQ24193_reg_prop prop, int *value)
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{
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u8 data;
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switch (prop) {
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case BQ24193_InputVoltageLimit: // Input voltage limit (mV).
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data = bq24193_get_reg(BQ24193_InputSource);
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data = (data & BQ24193_INCONFIG_VINDPM_MASK) >> 3;
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*value = 0;
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*value += ((data >> 0) & 1) ? 80 : 0;
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*value += ((data >> 1) & 1) ? 160 : 0;
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*value += ((data >> 2) & 1) ? 320 : 0;
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*value += ((data >> 3) & 1) ? 640 : 0;
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*value += 3880;
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break;
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case BQ24193_InputCurrentLimit: // Input current limit (mA).
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data = bq24193_get_reg(BQ24193_InputSource);
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data &= BQ24193_INCONFIG_INLIMIT_MASK;
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switch (data)
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{
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case 0:
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*value = 100;
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break;
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case 1:
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*value = 150;
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break;
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case 2:
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*value = 500;
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break;
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case 3:
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*value = 900;
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break;
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case 4:
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*value = 1200;
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break;
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case 5:
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*value = 1500;
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break;
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case 6:
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*value = 2000;
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break;
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case 7:
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*value = 3000;
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break;
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}
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break;
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case BQ24193_SystemMinimumVoltage: // Minimum system voltage limit (mV).
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data = bq24193_get_reg(BQ24193_PORConfig);
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*value = (data & BQ24193_PORCONFIG_SYSMIN_MASK) >> 1;
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*value *= 100;
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*value += 3000;
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break;
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case BQ24193_FastChargeCurrentLimit: // Fast charge current limit (mA).
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data = bq24193_get_reg(BQ24193_ChrgCurr);
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data = (data & BQ24193_CHRGCURR_ICHG_MASK) >> 2;
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*value = 0;
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*value += ((data >> 0) & 1) ? 64 : 0;
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*value += ((data >> 1) & 1) ? 128 : 0;
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*value += ((data >> 2) & 1) ? 256 : 0;
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*value += ((data >> 3) & 1) ? 512 : 0;
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*value += ((data >> 4) & 1) ? 1024 : 0;
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*value += ((data >> 5) & 1) ? 2048 : 0;
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*value += 512;
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data = bq24193_get_reg(BQ24193_ChrgCurr);
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data &= BQ24193_CHRGCURR_20PCT_MASK;
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if (data)
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*value = *value * 20 / 100; // Fast charge current limit is 20%.
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break;
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case BQ24193_ChargeVoltageLimit: // Charge voltage limit (mV).
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data = bq24193_get_reg(BQ24193_ChrgVolt);
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data = (data & BQ24193_CHRGVOLT_VREG) >> 2;
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*value = 0;
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*value += ((data >> 0) & 1) ? 16 : 0;
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*value += ((data >> 1) & 1) ? 32 : 0;
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*value += ((data >> 2) & 1) ? 64 : 0;
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*value += ((data >> 3) & 1) ? 128 : 0;
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*value += ((data >> 4) & 1) ? 256 : 0;
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*value += ((data >> 5) & 1) ? 512 : 0;
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*value += 3504;
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break;
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case BQ24193_RechargeThreshold: // Recharge voltage threshold less than voltage limit (mV).
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data = bq24193_get_reg(BQ24193_ChrgVolt);
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data &= BQ24193_IRTHERMAL_THERM_MASK;
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if (data)
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*value = 300;
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else
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*value = 100;
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break;
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case BQ24193_ThermalRegulation: // Thermal regulation threshold (oC).
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data = bq24193_get_reg(BQ24193_IRCompThermal);
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data &= BQ24193_IRTHERMAL_THERM_MASK;
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switch (data)
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{
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case 0:
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*value = 60;
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break;
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case 1:
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*value = 80;
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break;
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case 2:
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*value = 100;
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break;
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case 3:
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*value = 120;
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break;
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}
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break;
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case BQ24193_ChargeStatus: // 0: Not charging, 1: Pre-charge, 2: Fast charging, 3: Charge termination done
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data = bq24193_get_reg(BQ24193_Status);
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*value = (data & BQ24193_STATUS_CHRG_MASK) >> 4;
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break;
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case BQ24193_TempStatus: // 0: Normal, 2: Warm, 3: Cool, 5: Cold, 6: Hot.
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data = bq24193_get_reg(BQ24193_FaultReg);
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*value = data & BQ24193_FAULT_THERM_MASK;
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break;
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case BQ24193_DevID: // Dev ID.
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data = bq24193_get_reg(BQ24193_VendorPart);
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*value = data & BQ24193_VENDORPART_DEV_MASK;
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break;
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case BQ24193_ProductNumber: // Product number.
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data = bq24193_get_reg(BQ24193_VendorPart);
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*value = (data & BQ24193_VENDORPART_PN_MASK) >> 3;
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break;
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default:
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return -1;
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}
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return 0;
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}
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void bq24193_enable_charger()
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{
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u8 reg = bq24193_get_reg(BQ24193_PORConfig);
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reg &= ~BQ24193_PORCONFIG_CHGCONFIG_MASK;
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reg |= BQ24193_PORCONFIG_CHGCONFIG_CHARGER_EN;
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i2c_send_byte(I2C_1, BQ24193_I2C_ADDR, BQ24193_PORConfig, reg);
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}
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void bq24193_fake_battery_removal()
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{
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// Disable watchdog to keep BATFET disabled.
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u8 value = bq24193_get_reg(BQ24193_ChrgTermTimer);
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value &= ~BQ24193_CHRGTERM_WATCHDOG_MASK;
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i2c_send_byte(I2C_1, BQ24193_I2C_ADDR, BQ24193_ChrgTermTimer, value);
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// Force BATFET to disabled state. This disconnects the battery from the system.
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value = bq24193_get_reg(BQ24193_Misc);
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value |= BQ24193_MISC_BATFET_DI_MASK;
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i2c_send_byte(I2C_1, BQ24193_I2C_ADDR, BQ24193_Misc, value);
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}
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121
bdk/power/bq24193.h
Normal file
121
bdk/power/bq24193.h
Normal file
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/*
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* Battery charger driver for Nintendo Switch's TI BQ24193
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*
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* Copyright (c) 2018 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
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#ifndef __BQ24193_H_
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#define __BQ24193_H_
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#define BQ24193_I2C_ADDR 0x6B
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// REG 0 masks.
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#define BQ24193_INCONFIG_INLIMIT_MASK (7<<0)
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#define BQ24193_INCONFIG_VINDPM_MASK 0x78
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#define BQ24193_INCONFIG_HIZ_EN_MASK (1<<7)
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// REG 1 masks.
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#define BQ24193_PORCONFIG_BOOST_MASK (1<<0)
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#define BQ24193_PORCONFIG_SYSMIN_MASK (7<<1)
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#define BQ24193_PORCONFIG_CHGCONFIG_MASK (3<<4)
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#define BQ24193_PORCONFIG_CHGCONFIG_CHARGER_EN (1<<4)
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#define BQ24193_PORCONFIG_I2CWATCHDOG_MASK (1<<6)
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#define BQ24193_PORCONFIG_RESET_MASK (1<<7)
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// REG 2 masks.
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#define BQ24193_CHRGCURR_20PCT_MASK (1<<0)
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#define BQ24193_CHRGCURR_ICHG_MASK 0xFC
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// REG 3 masks.
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#define BQ24193_PRECHRG_ITERM 0x0F
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#define BQ24193_PRECHRG_IPRECHG 0xF0
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// REG 4 masks.
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#define BQ24193_CHRGVOLT_VTHRES (1<<0)
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#define BQ24193_CHRGVOLT_BATTLOW (1<<1)
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#define BQ24193_CHRGVOLT_VREG 0xFC
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// REG 5 masks.
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#define BQ24193_CHRGTERM_ISET_MASK (1<<0)
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#define BQ24193_CHRGTERM_CHGTIMER_MASK (3<<1)
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#define BQ24193_CHRGTERM_ENTIMER_MASK (1<<3)
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#define BQ24193_CHRGTERM_WATCHDOG_MASK (3<<4)
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#define BQ24193_CHRGTERM_TERM_ST_MASK (1<<6)
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#define BQ24193_CHRGTERM_TERM_EN_MASK (1<<7)
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// REG 6 masks.
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#define BQ24193_IRTHERMAL_THERM_MASK (3<<0)
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#define BQ24193_IRTHERMAL_VCLAMP_MASK (7<<2)
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#define BQ24193_IRTHERMAL_BATTCOMP_MASK (7<<5)
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// REG 7 masks.
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#define BQ24193_MISC_INT_MASK (3<<0)
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#define BQ24193_MISC_VSET_MASK (1<<4)
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#define BQ24193_MISC_BATFET_DI_MASK (1<<5)
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#define BQ24193_MISC_TMR2X_EN_MASK (1<<6)
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#define BQ24193_MISC_DPDM_EN_MASK (1<<7)
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// REG 8 masks.
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#define BQ24193_STATUS_VSYS_MASK (1<<0)
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#define BQ24193_STATUS_THERM_MASK (1<<1)
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#define BQ24193_STATUS_PG_MASK (1<<2)
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#define BQ24193_STATUS_DPM_MASK (1<<3)
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#define BQ24193_STATUS_CHRG_MASK (3<<4)
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#define BQ24193_STATUS_VBUS_MASK (3<<6)
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// REG 9 masks.
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#define BQ24193_FAULT_THERM_MASK (7<<0)
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#define BQ24193_FAULT_BATT_OVP_MASK (1<<3)
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#define BQ24193_FAULT_CHARGE_MASK (3<<4)
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#define BQ24193_FAULT_BOOST_MASK (1<<6)
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#define BQ24193_FAULT_WATCHDOG_MASK (1<<7)
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|
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// REG A masks.
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#define BQ24193_VENDORPART_DEV_MASK (3<<0)
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#define BQ24193_VENDORPART_PN_MASK (7<<3)
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|
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enum BQ24193_reg {
|
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BQ24193_InputSource = 0x00,
|
||||
BQ24193_PORConfig = 0x01,
|
||||
BQ24193_ChrgCurr = 0x02,
|
||||
BQ24193_PreChrgTerm = 0x03,
|
||||
BQ24193_ChrgVolt = 0x04,
|
||||
BQ24193_ChrgTermTimer = 0x05,
|
||||
BQ24193_IRCompThermal = 0x06,
|
||||
BQ24193_Misc = 0x07,
|
||||
BQ24193_Status = 0x08,
|
||||
BQ24193_FaultReg = 0x09,
|
||||
BQ24193_VendorPart = 0x0A,
|
||||
};
|
||||
|
||||
enum BQ24193_reg_prop {
|
||||
BQ24193_InputVoltageLimit, // REG 0.
|
||||
BQ24193_InputCurrentLimit, // REG 0.
|
||||
BQ24193_SystemMinimumVoltage, // REG 1.
|
||||
BQ24193_FastChargeCurrentLimit, // REG 2.
|
||||
BQ24193_ChargeVoltageLimit, // REG 4.
|
||||
BQ24193_RechargeThreshold, // REG 4.
|
||||
BQ24193_ThermalRegulation, // REG 6.
|
||||
BQ24193_ChargeStatus, // REG 8.
|
||||
BQ24193_TempStatus, // REG 9.
|
||||
BQ24193_DevID, // REG A.
|
||||
BQ24193_ProductNumber, // REG A.
|
||||
};
|
||||
|
||||
int bq24193_get_property(enum BQ24193_reg_prop prop, int *value);
|
||||
void bq24193_enable_charger();
|
||||
void bq24193_fake_battery_removal();
|
||||
|
||||
#endif /* __BQ24193_H_ */
|
||||
281
bdk/power/max17050.c
Normal file
281
bdk/power/max17050.c
Normal file
|
|
@ -0,0 +1,281 @@
|
|||
/*
|
||||
* Fuel gauge driver for Nintendo Switch's Maxim 17050
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics
|
||||
* MyungJoo Ham <myungjoo.ham@samsung.com>
|
||||
* Copyright (c) 2018 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*
|
||||
* This driver is based on max17040_battery.c
|
||||
*/
|
||||
|
||||
#include "max17050.h"
|
||||
#include <soc/i2c.h>
|
||||
#include <utils/util.h>
|
||||
|
||||
#define BASE_SNS_UOHM 5000
|
||||
|
||||
/* Status register bits */
|
||||
#define STATUS_POR_BIT BIT(1)
|
||||
#define STATUS_BST_BIT BIT(3)
|
||||
#define STATUS_VMN_BIT BIT(8)
|
||||
#define STATUS_TMN_BIT BIT(9)
|
||||
#define STATUS_SMN_BIT BIT(10)
|
||||
#define STATUS_BI_BIT BIT(11)
|
||||
#define STATUS_VMX_BIT BIT(12)
|
||||
#define STATUS_TMX_BIT BIT(13)
|
||||
#define STATUS_SMX_BIT BIT(14)
|
||||
#define STATUS_BR_BIT BIT(15)
|
||||
|
||||
#define VFSOC0_LOCK 0x0000
|
||||
#define VFSOC0_UNLOCK 0x0080
|
||||
|
||||
#define MAX17050_VMAX_TOLERANCE 50 /* 50 mV */
|
||||
|
||||
static u32 battery_voltage = 0;
|
||||
u32 max17050_get_cached_batt_volt()
|
||||
{
|
||||
return battery_voltage;
|
||||
}
|
||||
|
||||
static u16 max17050_get_reg(u8 reg)
|
||||
{
|
||||
u16 data = 0;
|
||||
|
||||
i2c_recv_buf_small((u8 *)&data, 2, I2C_1, MAXIM17050_I2C_ADDR, reg);
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
int max17050_get_property(enum MAX17050_reg reg, int *value)
|
||||
{
|
||||
u16 data;
|
||||
|
||||
switch (reg)
|
||||
{
|
||||
case MAX17050_Age: // Age (percent). Based on 100% x (FullCAP Register/DesignCap).
|
||||
data = max17050_get_reg(MAX17050_Age);
|
||||
*value = data >> 8; /* Show MSB. 1% increments */
|
||||
break;
|
||||
case MAX17050_Cycles: // Cycle count.
|
||||
*value = max17050_get_reg(MAX17050_Cycles);
|
||||
break;
|
||||
case MAX17050_MinVolt: // Voltage max/min
|
||||
data = max17050_get_reg(MAX17050_MinMaxVolt);
|
||||
*value = (data & 0xff) * 20; /* Voltage MIN. Units of 20mV */
|
||||
break;
|
||||
case MAX17050_MaxVolt: // Voltage max/min
|
||||
data = max17050_get_reg(MAX17050_MinMaxVolt);
|
||||
*value = (data >> 8) * 20; /* Voltage MAX. Units of LSB = 20mV */
|
||||
break;
|
||||
case MAX17050_V_empty: // Voltage min design.
|
||||
data = max17050_get_reg(MAX17050_V_empty);
|
||||
*value = (data >> 7) * 10; /* Units of LSB = 10mV */
|
||||
break;
|
||||
case MAX17050_VCELL: // Voltage now.
|
||||
data = max17050_get_reg(MAX17050_VCELL);
|
||||
*value = (data >> 3) * 625 / 1000; /* Units of LSB = 0.625mV */
|
||||
battery_voltage = *value;
|
||||
break;
|
||||
case MAX17050_AvgVCELL: // Voltage avg.
|
||||
data = max17050_get_reg(MAX17050_AvgVCELL);
|
||||
*value = (data >> 3) * 625 / 1000; /* Units of LSB = 0.625mV */
|
||||
break;
|
||||
case MAX17050_OCVInternal: // Voltage ocv.
|
||||
data = max17050_get_reg(MAX17050_OCVInternal);
|
||||
*value = (data >> 3) * 625 / 1000; /* Units of LSB = 0.625mV */
|
||||
break;
|
||||
case MAX17050_RepSOC: // Capacity %.
|
||||
*value = max17050_get_reg(MAX17050_RepSOC);
|
||||
break;
|
||||
case MAX17050_DesignCap: // Charge full design.
|
||||
data = max17050_get_reg(MAX17050_DesignCap);
|
||||
*value = data * (BASE_SNS_UOHM / MAX17050_BOARD_SNS_RESISTOR_UOHM) / MAX17050_BOARD_CGAIN;
|
||||
break;
|
||||
case MAX17050_FullCAP: // Charge full.
|
||||
data = max17050_get_reg(MAX17050_FullCAP);
|
||||
*value = data * (BASE_SNS_UOHM / MAX17050_BOARD_SNS_RESISTOR_UOHM) / MAX17050_BOARD_CGAIN;
|
||||
break;
|
||||
case MAX17050_RepCap: // Charge now.
|
||||
data = max17050_get_reg(MAX17050_RepCap);
|
||||
*value = data * (BASE_SNS_UOHM / MAX17050_BOARD_SNS_RESISTOR_UOHM) / MAX17050_BOARD_CGAIN;
|
||||
break;
|
||||
case MAX17050_TEMP: // Temp.
|
||||
data = max17050_get_reg(MAX17050_TEMP);
|
||||
*value = (s16)data;
|
||||
*value = *value * 10 / 256;
|
||||
break;
|
||||
case MAX17050_Current: // Current now.
|
||||
data = max17050_get_reg(MAX17050_Current);
|
||||
*value = (s16)data;
|
||||
*value *= 1562500 / (MAX17050_BOARD_SNS_RESISTOR_UOHM * MAX17050_BOARD_CGAIN);
|
||||
break;
|
||||
case MAX17050_AvgCurrent: // Current avg.
|
||||
data = max17050_get_reg(MAX17050_AvgCurrent);
|
||||
*value = (s16)data;
|
||||
*value *= 1562500 / (MAX17050_BOARD_SNS_RESISTOR_UOHM * MAX17050_BOARD_CGAIN);
|
||||
break;
|
||||
default:
|
||||
return -1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _max17050_write_verify_reg(u8 reg, u16 value)
|
||||
{
|
||||
int retries = 8;
|
||||
int ret;
|
||||
u16 read_value;
|
||||
|
||||
do
|
||||
{
|
||||
ret = i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, reg, (u8 *)&value, 2);
|
||||
read_value = max17050_get_reg(reg);
|
||||
if (read_value != value)
|
||||
{
|
||||
ret = -1;
|
||||
retries--;
|
||||
}
|
||||
} while (retries && read_value != value);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void _max17050_override_por(u8 reg, u16 value)
|
||||
{
|
||||
if (value)
|
||||
i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, reg, (u8 *)&value, 2);
|
||||
}
|
||||
|
||||
static void _max17050_load_new_capacity_params()
|
||||
{
|
||||
u16 fullcap, repSoc, dq_acc, dp_acc;
|
||||
|
||||
fullcap = 0x2476; // 4667mAh design capacity.
|
||||
dq_acc = 0x10bc; // From a healthy fuel gauge.
|
||||
dp_acc = 0x5e09; // =||=
|
||||
repSoc = 0x6400; // 100%.
|
||||
|
||||
_max17050_write_verify_reg(MAX17050_RemCap, fullcap);
|
||||
_max17050_write_verify_reg(MAX17050_RepCap, fullcap);
|
||||
|
||||
_max17050_write_verify_reg(MAX17050_dQacc, dq_acc);
|
||||
_max17050_write_verify_reg(MAX17050_dPacc, dp_acc);
|
||||
|
||||
_max17050_write_verify_reg(MAX17050_FullCAP, fullcap);
|
||||
//i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_DesignCap, (u8 *)&fullcap, 2);
|
||||
_max17050_write_verify_reg(MAX17050_FullCAPNom, fullcap);
|
||||
/* Update SOC register with new SOC */
|
||||
i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_RepSOC, (u8 *)&repSoc, 2);
|
||||
}
|
||||
|
||||
static void _max17050_reset_vfsoc0_reg()
|
||||
{
|
||||
u16 lockVal = 0;
|
||||
u16 vfSoc = 0x6440; // >100% for fully charged battery
|
||||
|
||||
lockVal = VFSOC0_UNLOCK;
|
||||
i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_VFSOC0Enable, (u8 *)&lockVal, 2);
|
||||
|
||||
_max17050_write_verify_reg(MAX17050_VFSOC0, vfSoc);
|
||||
|
||||
lockVal = VFSOC0_LOCK;
|
||||
i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_VFSOC0Enable, (u8 *)&lockVal, 2);
|
||||
}
|
||||
|
||||
static void _max17050_update_capacity_regs()
|
||||
{
|
||||
u16 value = 0x2476; // Set to 4667mAh design capacity.
|
||||
_max17050_write_verify_reg(MAX17050_FullCAP, value);
|
||||
_max17050_write_verify_reg(MAX17050_FullCAPNom, value);
|
||||
//i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_DesignCap, config->design_cap, 2);
|
||||
}
|
||||
|
||||
static void _max17050_write_config_regs()
|
||||
{
|
||||
u16 value = 0;
|
||||
|
||||
value = 0x7254;
|
||||
i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_CONFIG, (u8 *)&value, 2);
|
||||
value = 0x2473;
|
||||
i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_LearnCFG, (u8 *)&value, 2);
|
||||
//i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_FilterCFG, (u8 *)&value, 2)
|
||||
//i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_RelaxCFG, (u8 *)&value, 2)
|
||||
//i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_FullSOCThr, (u8 *)&value, 2)
|
||||
}
|
||||
|
||||
/*
|
||||
* Block write all the override values coming from platform data.
|
||||
* This function MUST be called before the POR initialization proceedure
|
||||
* specified by maxim.
|
||||
*/
|
||||
static void _max17050_override_por_values()
|
||||
{
|
||||
u16 dq_acc = 0x10bc; // From a healthy fuel gauge.
|
||||
u16 dp_acc = 0x5e09; // =||=
|
||||
|
||||
_max17050_override_por(MAX17050_dQacc, dq_acc);
|
||||
_max17050_override_por(MAX17050_dPacc, dp_acc);
|
||||
|
||||
//_max17050_override_por(MAX17050_RCOMP0, config->rcomp0); //0x58
|
||||
//_max17050_override_por(MAX17050_TempCo, config->tcompc0); //0x1b22
|
||||
|
||||
//u16 k_empty0 = 0x439;
|
||||
//_max17050_override_por(map, MAX17050_K_empty0, k_empty0); // Unknown cell data
|
||||
}
|
||||
|
||||
static void _max17050_set_por_bit(u16 value)
|
||||
{
|
||||
_max17050_write_verify_reg(MAX17050_STATUS, value);
|
||||
}
|
||||
|
||||
int max17050_fix_configuration()
|
||||
{
|
||||
/* Init phase, set the POR bit */
|
||||
_max17050_set_por_bit(STATUS_POR_BIT);
|
||||
|
||||
/* Override POR values */
|
||||
_max17050_override_por_values();
|
||||
/* After Power up, the MAX17050 requires 500ms in order
|
||||
* to perform signal debouncing and initial SOC reporting
|
||||
*/
|
||||
msleep(500);
|
||||
|
||||
/* Initialize configaration */
|
||||
_max17050_write_config_regs();
|
||||
|
||||
/* update capacity params */
|
||||
_max17050_update_capacity_regs();
|
||||
|
||||
/* delay must be atleast 350mS to allow VFSOC
|
||||
* to be calculated from the new configuration
|
||||
*/
|
||||
msleep(350);
|
||||
|
||||
/* reset vfsoc0 reg */
|
||||
_max17050_reset_vfsoc0_reg();
|
||||
|
||||
/* load new capacity params */
|
||||
_max17050_load_new_capacity_params();
|
||||
|
||||
/* Init complete, Clear the POR bit */
|
||||
//_max17050_set_por_bit(0); // Should we? Or let the switch to reconfigure POR?
|
||||
|
||||
// Sets POR, BI, BR.
|
||||
_max17050_set_por_bit(0x8801);
|
||||
|
||||
return 0;
|
||||
}
|
||||
137
bdk/power/max17050.h
Normal file
137
bdk/power/max17050.h
Normal file
|
|
@ -0,0 +1,137 @@
|
|||
/*
|
||||
* Fuel gauge driver for Nintendo Switch's Maxim 17050
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics
|
||||
* MyungJoo Ham <myungjoo.ham@samsung.com>
|
||||
* Copyright (c) 2018-2020 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __MAX17050_H_
|
||||
#define __MAX17050_H_
|
||||
|
||||
#include <utils/types.h>
|
||||
|
||||
/* Board default values */
|
||||
#define MAX17050_BOARD_CGAIN 2 /* Actual: 1.99993 */
|
||||
#define MAX17050_BOARD_SNS_RESISTOR_UOHM 5000 /* 0.005 Ohm */
|
||||
|
||||
#define MAX17050_STATUS_BattAbsent BIT(3)
|
||||
|
||||
/* Consider RepCap which is less then 10 units below FullCAP full */
|
||||
#define MAX17050_FULL_THRESHOLD 10
|
||||
|
||||
#define MAX17050_CHARACTERIZATION_DATA_SIZE 48
|
||||
|
||||
#define MAXIM17050_I2C_ADDR 0x36
|
||||
|
||||
enum MAX17050_reg {
|
||||
MAX17050_STATUS = 0x00,
|
||||
MAX17050_VALRT_Th = 0x01,
|
||||
MAX17050_TALRT_Th = 0x02,
|
||||
MAX17050_SALRT_Th = 0x03,
|
||||
MAX17050_AtRate = 0x04,
|
||||
MAX17050_RepCap = 0x05,
|
||||
MAX17050_RepSOC = 0x06,
|
||||
MAX17050_Age = 0x07,
|
||||
MAX17050_TEMP = 0x08,
|
||||
MAX17050_VCELL = 0x09,
|
||||
MAX17050_Current = 0x0A,
|
||||
MAX17050_AvgCurrent = 0x0B,
|
||||
|
||||
MAX17050_SOC = 0x0D,
|
||||
MAX17050_AvSOC = 0x0E,
|
||||
MAX17050_RemCap = 0x0F,
|
||||
MAX17050_FullCAP = 0x10,
|
||||
MAX17050_TTE = 0x11,
|
||||
MAX17050_QRTbl00 = 0x12,
|
||||
MAX17050_FullSOCThr = 0x13,
|
||||
MAX17050_RSLOW = 0x14,
|
||||
|
||||
MAX17050_AvgTA = 0x16,
|
||||
MAX17050_Cycles = 0x17,
|
||||
MAX17050_DesignCap = 0x18,
|
||||
MAX17050_AvgVCELL = 0x19,
|
||||
MAX17050_MinMaxTemp = 0x1A,
|
||||
MAX17050_MinMaxVolt = 0x1B,
|
||||
MAX17050_MinMaxCurr = 0x1C,
|
||||
MAX17050_CONFIG = 0x1D,
|
||||
MAX17050_ICHGTerm = 0x1E,
|
||||
MAX17050_AvCap = 0x1F,
|
||||
MAX17050_ManName = 0x20,
|
||||
MAX17050_DevName = 0x21,
|
||||
MAX17050_QRTbl10 = 0x22,
|
||||
MAX17050_FullCAPNom = 0x23,
|
||||
MAX17050_TempNom = 0x24,
|
||||
MAX17050_TempLim = 0x25,
|
||||
MAX17050_TempHot = 0x26,
|
||||
MAX17050_AIN = 0x27,
|
||||
MAX17050_LearnCFG = 0x28,
|
||||
MAX17050_FilterCFG = 0x29,
|
||||
MAX17050_RelaxCFG = 0x2A,
|
||||
MAX17050_MiscCFG = 0x2B,
|
||||
MAX17050_TGAIN = 0x2C,
|
||||
MAX17050_TOFF = 0x2D,
|
||||
MAX17050_CGAIN = 0x2E,
|
||||
MAX17050_COFF = 0x2F,
|
||||
|
||||
MAX17050_QRTbl20 = 0x32,
|
||||
MAX17050_SOC_empty = 0x33,
|
||||
MAX17050_T_empty = 0x34,
|
||||
MAX17050_FullCAP0 = 0x35,
|
||||
MAX17050_LAvg_empty = 0x36,
|
||||
MAX17050_FCTC = 0x37,
|
||||
MAX17050_RCOMP0 = 0x38,
|
||||
MAX17050_TempCo = 0x39,
|
||||
MAX17050_V_empty = 0x3A,
|
||||
MAX17050_K_empty0 = 0x3B,
|
||||
MAX17050_TaskPeriod = 0x3C,
|
||||
MAX17050_FSTAT = 0x3D,
|
||||
MAX17050_TIMER = 0x3E,
|
||||
MAX17050_SHDNTIMER = 0x3F,
|
||||
|
||||
MAX17050_QRTbl30 = 0x42,
|
||||
|
||||
MAX17050_dQacc = 0x45,
|
||||
MAX17050_dPacc = 0x46,
|
||||
|
||||
MAX17050_VFSOC0 = 0x48,
|
||||
|
||||
Max17050_QH0 = 0x4C,
|
||||
MAX17050_QH = 0x4D,
|
||||
MAX17050_QL = 0x4E,
|
||||
|
||||
MAX17050_MinVolt = 0x50, // Custom ID. Not to be sent to i2c.
|
||||
MAX17050_MaxVolt = 0x51, // Custom ID. Not to be sent to i2c.
|
||||
|
||||
MAX17050_VFSOC0Enable = 0x60,
|
||||
MAX17050_MODELEnable1 = 0x62,
|
||||
MAX17050_MODELEnable2 = 0x63,
|
||||
|
||||
MAX17050_MODELChrTbl = 0x80,
|
||||
|
||||
MAX17050_OCV = 0xEE,
|
||||
|
||||
MAX17050_OCVInternal = 0xFB,
|
||||
|
||||
MAX17050_VFSOC = 0xFF,
|
||||
};
|
||||
|
||||
int max17050_get_property(enum MAX17050_reg reg, int *value);
|
||||
int max17050_fix_configuration();
|
||||
u32 max17050_get_cached_batt_volt();
|
||||
|
||||
#endif /* __MAX17050_H_ */
|
||||
380
bdk/power/max77620.h
Normal file
380
bdk/power/max77620.h
Normal file
|
|
@ -0,0 +1,380 @@
|
|||
/*
|
||||
* Defining registers address and its bit definitions of MAX77620 and MAX20024
|
||||
*
|
||||
* Copyright (c) 2019-2020 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _MFD_MAX77620_H_
|
||||
#define _MFD_MAX77620_H_
|
||||
|
||||
#define MAX77620_I2C_ADDR 0x3C
|
||||
|
||||
/* GLOBAL, PMIC, GPIO, FPS, ONOFFC, CID Registers */
|
||||
#define MAX77620_REG_CNFGGLBL1 0x00
|
||||
#define MAX77620_CNFGGLBL1_LBRSTEN BIT(0)
|
||||
#define MAX77620_CNFGGLBL1_LBDAC_MASK 0x0E
|
||||
#define MAX77620_CNFGGLBL1_LBDAC_2700 (0 << 1)
|
||||
#define MAX77620_CNFGGLBL1_LBDAC_2800 (1 << 1)
|
||||
#define MAX77620_CNFGGLBL1_LBDAC_2900 (2 << 1)
|
||||
#define MAX77620_CNFGGLBL1_LBDAC_3000 (3 << 1)
|
||||
#define MAX77620_CNFGGLBL1_LBDAC_3100 (4 << 1)
|
||||
#define MAX77620_CNFGGLBL1_LBDAC_3200 (5 << 1)
|
||||
#define MAX77620_CNFGGLBL1_LBDAC_3300 (6 << 1)
|
||||
#define MAX77620_CNFGGLBL1_LBDAC_3400 (7 << 1)
|
||||
#define MAX77620_CNFGGLBL1_LBHYST_100 (0 << 4)
|
||||
#define MAX77620_CNFGGLBL1_LBHYST_200 (1 << 4)
|
||||
#define MAX77620_CNFGGLBL1_LBHYST_300 (2 << 4)
|
||||
#define MAX77620_CNFGGLBL1_LBHYST_400 (3 << 4)
|
||||
#define MAX77620_CNFGGLBL1_MPPLD BIT(6)
|
||||
#define MAX77620_CNFGGLBL1_LBDAC_EN BIT(7)
|
||||
|
||||
#define MAX77620_REG_CNFGGLBL2 0x01
|
||||
#define MAX77620_TWD_MASK 0x3
|
||||
#define MAX77620_TWD_2s 0x0
|
||||
#define MAX77620_TWD_16s 0x1
|
||||
#define MAX77620_TWD_64s 0x2
|
||||
#define MAX77620_TWD_128s 0x3
|
||||
#define MAX77620_WDTEN BIT(2)
|
||||
#define MAX77620_WDTSLPC BIT(3)
|
||||
#define MAX77620_WDTOFFC BIT(4)
|
||||
#define MAX77620_GLBL_LPM BIT(5)
|
||||
#define MAX77620_I2CTWD_MASK 0xC0
|
||||
#define MAX77620_I2CTWD_DISABLED 0x00
|
||||
#define MAX77620_I2CTWD_1_33ms 0x40
|
||||
#define MAX77620_I2CTWD_35_7ms 0x80
|
||||
#define MAX77620_I2CTWD_41_7ms 0xC0
|
||||
|
||||
#define MAX77620_REG_CNFGGLBL3 0x02
|
||||
#define MAX77620_WDTC_MASK 0x3
|
||||
|
||||
#define MAX77620_REG_CNFG1_32K 0x03
|
||||
#define MAX77620_CNFG1_PWR_MD_32K_MASK 0x3
|
||||
#define MAX77620_CNFG1_32K_OUT0_EN BIT(2)
|
||||
#define MAX77620_CNFG1_32KLOAD_MASK 0x30
|
||||
#define MAX77620_CNFG1_32K_OK BIT(7)
|
||||
|
||||
#define MAX77620_REG_CNFGBBC 0x04
|
||||
#define MAX77620_CNFGBBC_ENABLE BIT(0)
|
||||
#define MAX77620_CNFGBBC_CURRENT_MASK 0x06
|
||||
#define MAX77620_CNFGBBC_CURRENT_SHIFT 1
|
||||
#define MAX77620_CNFGBBC_VOLTAGE_MASK 0x18
|
||||
#define MAX77620_CNFGBBC_VOLTAGE_SHIFT 3
|
||||
#define MAX77620_CNFGBBC_LOW_CURRENT_DISABLE BIT(5)
|
||||
#define MAX77620_CNFGBBC_RESISTOR_MASK 0xC0
|
||||
#define MAX77620_CNFGBBC_RESISTOR_SHIFT 6
|
||||
#define MAX77620_CNFGBBC_RESISTOR_100 (0 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
|
||||
#define MAX77620_CNFGBBC_RESISTOR_1K (1 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
|
||||
#define MAX77620_CNFGBBC_RESISTOR_3K (2 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
|
||||
#define MAX77620_CNFGBBC_RESISTOR_6K (3 << MAX77620_CNFGBBC_RESISTOR_SHIFT)
|
||||
|
||||
#define MAX77620_REG_IRQTOP 0x05
|
||||
#define MAX77620_REG_IRQTOPM 0x0D
|
||||
#define MAX77620_IRQ_TOP_ONOFF_MASK BIT(1)
|
||||
#define MAX77620_IRQ_TOP_32K_MASK BIT(2)
|
||||
#define MAX77620_IRQ_TOP_RTC_MASK BIT(3)
|
||||
#define MAX77620_IRQ_TOP_GPIO_MASK BIT(4)
|
||||
#define MAX77620_IRQ_TOP_LDO_MASK BIT(5)
|
||||
#define MAX77620_IRQ_TOP_SD_MASK BIT(6)
|
||||
#define MAX77620_IRQ_TOP_GLBL_MASK BIT(7)
|
||||
|
||||
#define MAX77620_REG_INTLBT 0x06
|
||||
#define MAX77620_REG_INTENLBT 0x0E
|
||||
#define MAX77620_IRQ_GLBLM_MASK BIT(0)
|
||||
#define MAX77620_IRQ_TJALRM2_MASK BIT(1)
|
||||
#define MAX77620_IRQ_TJALRM1_MASK BIT(2)
|
||||
#define MAX77620_IRQ_LBM_MASK BIT(3)
|
||||
|
||||
#define MAX77620_REG_IRQSD 0x07
|
||||
#define MAX77620_REG_IRQMASKSD 0x0F
|
||||
#define MAX77620_IRQSD_PFI_SD3 BIT(4)
|
||||
#define MAX77620_IRQSD_PFI_SD2 BIT(5)
|
||||
#define MAX77620_IRQSD_PFI_SD1 BIT(6)
|
||||
#define MAX77620_IRQSD_PFI_SD0 BIT(7)
|
||||
|
||||
#define MAX77620_REG_IRQ_LVL2_L0_7 0x08 // LDO number that irq occured.
|
||||
#define MAX77620_REG_IRQ_MSK_L0_7 0x10
|
||||
#define MAX77620_REG_IRQ_LVL2_L8 0x09 // LDO number that irq occured. Only bit0: LDO8 is valid.
|
||||
#define MAX77620_REG_IRQ_MSK_L8 0x11
|
||||
#define MAX77620_REG_IRQ_LVL2_GPIO 0x0A // Edge detection interrupt.
|
||||
|
||||
#define MAX77620_REG_ONOFFIRQ 0x0B
|
||||
#define MAX77620_REG_ONOFFIRQM 0x12
|
||||
#define MAX77620_ONOFFIRQ_MRWRN BIT(0)
|
||||
#define MAX77620_ONOFFIRQ_EN0_1SEC BIT(1)
|
||||
#define MAX77620_ONOFFIRQ_EN0_F BIT(2)
|
||||
#define MAX77620_ONOFFIRQ_EN0_R BIT(3)
|
||||
#define MAX77620_ONOFFIRQ_LID_F BIT(4)
|
||||
#define MAX77620_ONOFFIRQ_LID_R BIT(5)
|
||||
#define MAX77620_ONOFFIRQ_ACOK_F BIT(6)
|
||||
#define MAX77620_ONOFFIRQ_ACOK_R BIT(7)
|
||||
|
||||
#define MAX77620_REG_NVERC 0x0C // Shutdown reason (non-volatile).
|
||||
#define MAX77620_NVERC_SHDN BIT(0)
|
||||
#define MAX77620_NVERC_WTCHDG BIT(1)
|
||||
#define MAX77620_NVERC_HDRST BIT(2)
|
||||
#define MAX77620_NVERC_TOVLD BIT(3)
|
||||
#define MAX77620_NVERC_MBLSD BIT(4)
|
||||
#define MAX77620_NVERC_MBO BIT(5)
|
||||
#define MAX77620_NVERC_MBU BIT(6)
|
||||
#define MAX77620_NVERC_RSTIN BIT(7)
|
||||
|
||||
#define MAX77620_REG_STATLBT 0x13
|
||||
#define MAX77620_REG_STATSD 0x14
|
||||
|
||||
#define MAX77620_REG_ONOFFSTAT 0x15
|
||||
#define MAX77620_ONOFFSTAT_LID BIT(0)
|
||||
#define MAX77620_ONOFFSTAT_ACOK BIT(1)
|
||||
#define MAX77620_ONOFFSTAT_EN0 BIT(2)
|
||||
|
||||
/* SD and LDO Registers */
|
||||
#define MAX77620_REG_SD0 0x16
|
||||
#define MAX77620_REG_SD1 0x17
|
||||
#define MAX77620_REG_SD2 0x18
|
||||
#define MAX77620_REG_SD3 0x19
|
||||
#define MAX77620_REG_SD4 0x1A
|
||||
#define MAX77620_REG_DVSSD0 0x1B
|
||||
#define MAX77620_REG_DVSSD1 0x1C
|
||||
#define MAX77620_SDX_VOLT_MASK 0xFF
|
||||
#define MAX77620_SD0_VOLT_MASK 0x3F
|
||||
#define MAX77620_SD1_VOLT_MASK 0x7F
|
||||
#define MAX77620_LDO_VOLT_MASK 0x3F
|
||||
|
||||
#define MAX77620_REG_SD0_CFG 0x1D
|
||||
#define MAX77620_REG_SD1_CFG 0x1E
|
||||
#define MAX77620_REG_SD2_CFG 0x1F
|
||||
#define MAX77620_REG_SD3_CFG 0x20
|
||||
#define MAX77620_REG_SD4_CFG 0x21
|
||||
#define MAX77620_SD_SR_MASK 0xC0
|
||||
#define MAX77620_SD_SR_SHIFT 6
|
||||
#define MAX77620_SD_POWER_MODE_MASK 0x30
|
||||
#define MAX77620_SD_POWER_MODE_SHIFT 4
|
||||
#define MAX77620_SD_CFG1_ADE_MASK BIT(3)
|
||||
#define MAX77620_SD_CFG1_ADE_DISABLE 0
|
||||
#define MAX77620_SD_CFG1_ADE_ENABLE BIT(3)
|
||||
#define MAX77620_SD_FPWM_MASK 0x04
|
||||
#define MAX77620_SD_FPWM_SHIFT 2
|
||||
#define MAX77620_SD_FSRADE_MASK 0x01
|
||||
#define MAX77620_SD_FSRADE_SHIFT 0
|
||||
#define MAX77620_SD_CFG1_FPWM_SD_MASK BIT(2)
|
||||
#define MAX77620_SD_CFG1_FPWM_SD_SKIP 0
|
||||
#define MAX77620_SD_CFG1_FPWM_SD_FPWM BIT(2)
|
||||
#define MAX77620_SD_CFG1_MPOK_MASK BIT(1)
|
||||
#define MAX77620_SD_CFG1_FSRADE_SD_MASK BIT(0)
|
||||
#define MAX77620_SD_CFG1_FSRADE_SD_DISABLE 0
|
||||
#define MAX77620_SD_CFG1_FSRADE_SD_ENABLE BIT(0)
|
||||
|
||||
#define MAX77620_REG_SD_CFG2 0x22
|
||||
#define MAX77620_SD_CNF2_RSVD BIT(0)
|
||||
#define MAX77620_SD_CNF2_ROVS_EN_SD1 BIT(1)
|
||||
#define MAX77620_SD_CNF2_ROVS_EN_SD0 BIT(2)
|
||||
|
||||
#define MAX77620_REG_LDO0_CFG 0x23
|
||||
#define MAX77620_REG_LDO0_CFG2 0x24
|
||||
#define MAX77620_REG_LDO1_CFG 0x25
|
||||
#define MAX77620_REG_LDO1_CFG2 0x26
|
||||
#define MAX77620_REG_LDO2_CFG 0x27
|
||||
#define MAX77620_REG_LDO2_CFG2 0x28
|
||||
#define MAX77620_REG_LDO3_CFG 0x29
|
||||
#define MAX77620_REG_LDO3_CFG2 0x2A
|
||||
#define MAX77620_REG_LDO4_CFG 0x2B
|
||||
#define MAX77620_REG_LDO4_CFG2 0x2C
|
||||
#define MAX77620_REG_LDO5_CFG 0x2D
|
||||
#define MAX77620_REG_LDO5_CFG2 0x2E
|
||||
#define MAX77620_REG_LDO6_CFG 0x2F
|
||||
#define MAX77620_REG_LDO6_CFG2 0x30
|
||||
#define MAX77620_REG_LDO7_CFG 0x31
|
||||
#define MAX77620_REG_LDO7_CFG2 0x32
|
||||
#define MAX77620_REG_LDO8_CFG 0x33
|
||||
#define MAX77620_REG_LDO8_CFG2 0x34
|
||||
/*! LDO CFG */
|
||||
#define MAX77620_LDO_POWER_MODE_SHIFT 6
|
||||
#define MAX77620_LDO_POWER_MODE_MASK (3 << MAX77620_LDO_POWER_MODE_SHIFT)
|
||||
#define MAX77620_POWER_MODE_NORMAL 3
|
||||
#define MAX77620_POWER_MODE_LPM 2
|
||||
#define MAX77620_POWER_MODE_GLPM 1
|
||||
#define MAX77620_POWER_MODE_DISABLE 0
|
||||
/*! LDO CFG2 */
|
||||
#define MAX77620_LDO_CFG2_SS_MASK (1 << 0)
|
||||
#define MAX77620_LDO_CFG2_SS_FAST (0 << 0)
|
||||
#define MAX77620_LDO_CFG2_SS_SLOW (1 << 0)
|
||||
#define MAX77620_LDO_CFG2_ADE_MASK (1 << 1)
|
||||
#define MAX77620_LDO_CFG2_ADE_DISABLE (0 << 1)
|
||||
#define MAX77620_LDO_CFG2_ADE_ENABLE (1 << 1)
|
||||
#define MAX77620_LDO_CFG2_MPOK_MASK BIT(2)
|
||||
#define MAX77620_LDO_CFG2_POK_MASK BIT(3)
|
||||
#define MAX77620_LDO_CFG2_COMP_SHIFT 4
|
||||
#define MAX77620_LDO_CFG2_COMP_MASK (3 << MAX77620_LDO_COMP_SHIFT)
|
||||
#define MAX77620_LDO_CFG2_COMP_SLOW 3
|
||||
#define MAX77620_LDO_CFG2_COMP_MID_SLOW 2
|
||||
#define MAX77620_LDO_CFG2_COMP_MID_FAST 1
|
||||
#define MAX77620_LDO_CFG2_COMP_FAST 0
|
||||
#define MAX77620_LDO_CFG2_ALPM_EN_MASK BIT(6)
|
||||
#define MAX77620_LDO_CFG2_OVCLMP_MASK BIT(7)
|
||||
|
||||
#define MAX77620_REG_LDO_CFG3 0x35
|
||||
#define MAX77620_LDO_BIAS_EN BIT(0)
|
||||
#define MAX77620_TRACK4_SHIFT 5
|
||||
#define MAX77620_TRACK4_MASK (1 << MAX77620_TRACK4_SHIFT)
|
||||
|
||||
#define MAX77620_REG_GPIO0 0x36
|
||||
#define MAX77620_REG_GPIO1 0x37
|
||||
#define MAX77620_REG_GPIO2 0x38
|
||||
#define MAX77620_REG_GPIO3 0x39
|
||||
#define MAX77620_REG_GPIO4 0x3A
|
||||
#define MAX77620_REG_GPIO5 0x3B
|
||||
#define MAX77620_REG_GPIO6 0x3C
|
||||
#define MAX77620_REG_GPIO7 0x3D
|
||||
#define MAX77620_CNFG_GPIO_DRV_MASK (1 << 0)
|
||||
#define MAX77620_CNFG_GPIO_DRV_PUSHPULL (1 << 0)
|
||||
#define MAX77620_CNFG_GPIO_DRV_OPENDRAIN (0 << 0)
|
||||
#define MAX77620_CNFG_GPIO_DIR_MASK (1 << 1)
|
||||
#define MAX77620_CNFG_GPIO_DIR_INPUT (1 << 1)
|
||||
#define MAX77620_CNFG_GPIO_DIR_OUTPUT (0 << 1)
|
||||
#define MAX77620_CNFG_GPIO_INPUT_VAL_MASK (1 << 2)
|
||||
#define MAX77620_CNFG_GPIO_OUTPUT_VAL_MASK (1 << 3)
|
||||
#define MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH (1 << 3)
|
||||
#define MAX77620_CNFG_GPIO_OUTPUT_VAL_LOW (0 << 3)
|
||||
#define MAX77620_CNFG_GPIO_INT_MASK (0x3 << 4)
|
||||
#define MAX77620_CNFG_GPIO_INT_FALLING (1 << 4)
|
||||
#define MAX77620_CNFG_GPIO_INT_RISING (1 << 5)
|
||||
#define MAX77620_CNFG_GPIO_DBNC_MASK (0x3 << 6)
|
||||
#define MAX77620_CNFG_GPIO_DBNC_None (0x0 << 6)
|
||||
#define MAX77620_CNFG_GPIO_DBNC_8ms (0x1 << 6)
|
||||
#define MAX77620_CNFG_GPIO_DBNC_16ms (0x2 << 6)
|
||||
#define MAX77620_CNFG_GPIO_DBNC_32ms (0x3 << 6)
|
||||
#define MAX77620_GPIO_OUTPUT_DISABLE 0
|
||||
#define MAX77620_GPIO_OUTPUT_ENABLE 1
|
||||
|
||||
#define MAX77620_REG_PUE_GPIO 0x3E // Gpio Pullup resistor enable.
|
||||
#define MAX77620_REG_PDE_GPIO 0x3F // Gpio Pulldown resistor enable.
|
||||
|
||||
#define MAX77620_REG_AME_GPIO 0x40 // Gpio pinmuxing. Clear bits are Standard GPIO.
|
||||
|
||||
#define MAX77620_REG_ONOFFCNFG1 0x41
|
||||
#define MAX20024_ONOFFCNFG1_CLRSE 0x18
|
||||
#define MAX77620_ONOFFCNFG1_PWR_OFF BIT(1)
|
||||
#define MAX77620_ONOFFCNFG1_SLPEN BIT(2)
|
||||
#define MAX77620_ONOFFCNFG1_MRT_SHIFT 0x3
|
||||
#define MAX77620_ONOFFCNFG1_MRT_MASK 0x38
|
||||
#define MAX77620_ONOFFCNFG1_RSVD BIT(6)
|
||||
#define MAX77620_ONOFFCNFG1_SFT_RST BIT(7)
|
||||
|
||||
#define MAX77620_REG_ONOFFCNFG2 0x42
|
||||
#define MAX77620_ONOFFCNFG2_WK_EN0 BIT(0)
|
||||
#define MAX77620_ONOFFCNFG2_WK_ALARM2 BIT(1)
|
||||
#define MAX77620_ONOFFCNFG2_WK_ALARM1 BIT(2)
|
||||
#define MAX77620_ONOFFCNFG2_WK_MBATT BIT(3) // MBATT event generates a wakeup signal. use it in android/l4t?
|
||||
#define MAX77620_ONOFFCNFG2_WK_ACOK BIT(4)
|
||||
#define MAX77620_ONOFFCNFG2_SLP_LPM_MSK BIT(5)
|
||||
#define MAX77620_ONOFFCNFG2_WD_RST_WK BIT(6)
|
||||
#define MAX77620_ONOFFCNFG2_SFT_RST_WK BIT(7)
|
||||
|
||||
/* FPS Registers */
|
||||
#define MAX77620_REG_FPS_CFG0 0x43 // FPS0.
|
||||
#define MAX77620_REG_FPS_CFG1 0x44 // FPS1.
|
||||
#define MAX77620_REG_FPS_CFG2 0x45 // FPS2.
|
||||
#define MAX77620_FPS_ENFPS_SW_MASK 0x01
|
||||
#define MAX77620_FPS_ENFPS_SW 0x01
|
||||
#define MAX77620_FPS_EN_SRC_SHIFT 1
|
||||
#define MAX77620_FPS_EN_SRC_MASK 0x06
|
||||
#define MAX77620_FPS_TIME_PERIOD_SHIFT 3
|
||||
#define MAX77620_FPS_TIME_PERIOD_MASK 0x38
|
||||
|
||||
#define MAX77620_REG_FPS_LDO0 0x46
|
||||
#define MAX77620_REG_FPS_LDO1 0x47
|
||||
#define MAX77620_REG_FPS_LDO2 0x48
|
||||
#define MAX77620_REG_FPS_LDO3 0x49
|
||||
#define MAX77620_REG_FPS_LDO4 0x4A
|
||||
#define MAX77620_REG_FPS_LDO5 0x4B
|
||||
#define MAX77620_REG_FPS_LDO6 0x4C
|
||||
#define MAX77620_REG_FPS_LDO7 0x4D
|
||||
#define MAX77620_REG_FPS_LDO8 0x4E
|
||||
#define MAX77620_REG_FPS_SD0 0x4F
|
||||
#define MAX77620_REG_FPS_SD1 0x50
|
||||
#define MAX77620_REG_FPS_SD2 0x51
|
||||
#define MAX77620_REG_FPS_SD3 0x52
|
||||
#define MAX77620_REG_FPS_SD4 0x53
|
||||
#define MAX77620_REG_FPS_GPIO1 0x54
|
||||
#define MAX77620_REG_FPS_GPIO2 0x55
|
||||
#define MAX77620_REG_FPS_GPIO3 0x56
|
||||
#define MAX77620_REG_FPS_RSO 0x57
|
||||
#define MAX77620_FPS_PD_PERIOD_SHIFT 0
|
||||
#define MAX77620_FPS_PD_PERIOD_MASK 0x07
|
||||
#define MAX77620_FPS_PU_PERIOD_SHIFT 3
|
||||
#define MAX77620_FPS_PU_PERIOD_MASK 0x38
|
||||
#define MAX77620_FPS_SRC_SHIFT 6
|
||||
#define MAX77620_FPS_SRC_MASK 0xC0
|
||||
|
||||
#define MAX77620_FPS_COUNT 3
|
||||
#define MAX77620_FPS_PERIOD_MIN_US 40
|
||||
#define MAX77620_FPS_PERIOD_MAX_US 2560
|
||||
|
||||
#define MAX77620_REG_CID0 0x58
|
||||
#define MAX77620_REG_CID1 0x59
|
||||
#define MAX77620_REG_CID2 0x5A
|
||||
#define MAX77620_REG_CID3 0x5B
|
||||
#define MAX77620_REG_CID4 0x5C // OTP version.
|
||||
#define MAX77620_REG_CID5 0x5D
|
||||
#define MAX77620_CID_DIDO_MASK 0xF
|
||||
#define MAX77620_CID_DIDO_SHIFT 0
|
||||
#define MAX77620_CID_DIDM_MASK 0xF0
|
||||
#define MAX77620_CID_DIDM_SHIFT 4
|
||||
|
||||
/* Device Identification Metal */
|
||||
#define MAX77620_CID5_DIDM(n) (((n) >> 4) & 0xF)
|
||||
/* Device Indentification OTP */
|
||||
#define MAX77620_CID5_DIDO(n) ((n) & 0xF)
|
||||
|
||||
#define MAX77620_REG_DVSSD4 0x5E
|
||||
#define MAX20024_REG_MAX_ADD 0x70
|
||||
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE0 BIT(0)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE1 BIT(1)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE2 BIT(2)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE3 BIT(3)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE4 BIT(4)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE5 BIT(5)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE6 BIT(6)
|
||||
#define MAX77620_IRQ_LVL2_GPIO_EDGE7 BIT(7)
|
||||
|
||||
/* Interrupts */
|
||||
enum {
|
||||
MAX77620_IRQ_TOP_GLBL, /* Low-Battery */
|
||||
MAX77620_IRQ_TOP_SD, /* SD power fail */
|
||||
MAX77620_IRQ_TOP_LDO, /* LDO power fail */
|
||||
MAX77620_IRQ_TOP_GPIO, /* TOP GPIO internal int to MAX77620 */
|
||||
MAX77620_IRQ_TOP_RTC, /* RTC */
|
||||
MAX77620_IRQ_TOP_32K, /* 32kHz oscillator */
|
||||
MAX77620_IRQ_TOP_ONOFF, /* ON/OFF oscillator */
|
||||
MAX77620_IRQ_LBT_MBATLOW, /* Thermal alarm status, > 120C */
|
||||
MAX77620_IRQ_LBT_TJALRM1, /* Thermal alarm status, > 120C */
|
||||
MAX77620_IRQ_LBT_TJALRM2, /* Thermal alarm status, > 140C */
|
||||
};
|
||||
|
||||
/* GPIOs */
|
||||
enum {
|
||||
MAX77620_GPIO0,
|
||||
MAX77620_GPIO1,
|
||||
MAX77620_GPIO2,
|
||||
MAX77620_GPIO3,
|
||||
MAX77620_GPIO4,
|
||||
MAX77620_GPIO5,
|
||||
MAX77620_GPIO6,
|
||||
MAX77620_GPIO7,
|
||||
MAX77620_GPIO_NR,
|
||||
};
|
||||
|
||||
/* FPS Source */
|
||||
enum max77620_fps_src {
|
||||
MAX77620_FPS_SRC_0,
|
||||
MAX77620_FPS_SRC_1,
|
||||
MAX77620_FPS_SRC_2,
|
||||
MAX77620_FPS_SRC_NONE,
|
||||
MAX77620_FPS_SRC_DEF,
|
||||
};
|
||||
|
||||
#endif /* _MFD_MAX77620_H_ */
|
||||
339
bdk/power/max7762x.c
Normal file
339
bdk/power/max7762x.c
Normal file
|
|
@ -0,0 +1,339 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2019-2020 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <power/max7762x.h>
|
||||
#include <power/max77620.h>
|
||||
#include <power/max77812.h>
|
||||
#include <soc/fuse.h>
|
||||
#include <soc/i2c.h>
|
||||
#include <soc/t210.h>
|
||||
#include <utils/util.h>
|
||||
|
||||
#define REGULATOR_SD 0
|
||||
#define REGULATOR_LDO 1
|
||||
#define REGULATOR_BC0 2
|
||||
#define REGULATOR_BC1 3
|
||||
|
||||
typedef struct _max77620_fps_t
|
||||
{
|
||||
u8 fps_addr;
|
||||
u8 fps_src;
|
||||
u8 pd_period;
|
||||
u8 pu_period;
|
||||
} max77620_fps_t;
|
||||
|
||||
typedef struct _max77621_ctrl_t
|
||||
{
|
||||
u8 ctrl1_por;
|
||||
u8 ctrl1_hos;
|
||||
u8 ctrl2_por;
|
||||
u8 ctrl2_hos;
|
||||
} max77621_ctrl_t;
|
||||
|
||||
typedef struct _max77812_ctrl_t
|
||||
{
|
||||
u8 mask;
|
||||
u8 shift;
|
||||
u8 rsvd0;
|
||||
u8 rsvd1;
|
||||
} max77812_en_t;
|
||||
|
||||
typedef struct _max77620_regulator_t
|
||||
{
|
||||
const char *name;
|
||||
|
||||
u32 uv_step;
|
||||
u32 uv_min;
|
||||
u32 uv_default;
|
||||
u32 uv_max;
|
||||
|
||||
u8 type;
|
||||
u8 volt_addr;
|
||||
u8 cfg_addr;
|
||||
u8 volt_mask;
|
||||
|
||||
union {
|
||||
max77620_fps_t fps;
|
||||
max77621_ctrl_t ctrl;
|
||||
max77812_en_t enable;
|
||||
};
|
||||
} max77620_regulator_t;
|
||||
|
||||
static const max77620_regulator_t _pmic_regulators[] = {
|
||||
{ "sd0", 12500, 600000, 625000, 1400000, REGULATOR_SD, MAX77620_REG_SD0, MAX77620_REG_SD0_CFG, MAX77620_SD0_VOLT_MASK, {{ MAX77620_REG_FPS_SD0, 1, 7, 1 }} },
|
||||
{ "sd1", 12500, 600000, 1125000, 1250000, REGULATOR_SD, MAX77620_REG_SD1, MAX77620_REG_SD1_CFG, MAX77620_SD1_VOLT_MASK, {{ MAX77620_REG_FPS_SD1, 0, 1, 5 }} },
|
||||
{ "sd2", 12500, 600000, 1325000, 1350000, REGULATOR_SD, MAX77620_REG_SD2, MAX77620_REG_SD2_CFG, MAX77620_SDX_VOLT_MASK, {{ MAX77620_REG_FPS_SD2, 1, 5, 2 }} },
|
||||
{ "sd3", 12500, 600000, 1800000, 1800000, REGULATOR_SD, MAX77620_REG_SD3, MAX77620_REG_SD3_CFG, MAX77620_SDX_VOLT_MASK, {{ MAX77620_REG_FPS_SD3, 0, 3, 3 }} },
|
||||
{ "ldo0", 25000, 800000, 1200000, 1200000, REGULATOR_LDO, MAX77620_REG_LDO0_CFG, MAX77620_REG_LDO0_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO0, 3, 7, 0 }} },
|
||||
{ "ldo1", 25000, 800000, 1050000, 1050000, REGULATOR_LDO, MAX77620_REG_LDO1_CFG, MAX77620_REG_LDO1_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO1, 3, 7, 0 }} },
|
||||
{ "ldo2", 50000, 800000, 1800000, 3300000, REGULATOR_LDO, MAX77620_REG_LDO2_CFG, MAX77620_REG_LDO2_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO2, 3, 7, 0 }} },
|
||||
{ "ldo3", 50000, 800000, 3100000, 3100000, REGULATOR_LDO, MAX77620_REG_LDO3_CFG, MAX77620_REG_LDO3_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO3, 3, 7, 0 }} },
|
||||
{ "ldo4", 12500, 800000, 850000, 1000000, REGULATOR_LDO, MAX77620_REG_LDO4_CFG, MAX77620_REG_LDO4_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO4, 0, 7, 1 }} },
|
||||
{ "ldo5", 50000, 800000, 1800000, 1800000, REGULATOR_LDO, MAX77620_REG_LDO5_CFG, MAX77620_REG_LDO5_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO5, 3, 7, 0 }} },
|
||||
{ "ldo6", 50000, 800000, 2900000, 2900000, REGULATOR_LDO, MAX77620_REG_LDO6_CFG, MAX77620_REG_LDO6_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO6, 3, 7, 0 }} },
|
||||
{ "ldo7", 50000, 800000, 1050000, 1050000, REGULATOR_LDO, MAX77620_REG_LDO7_CFG, MAX77620_REG_LDO7_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO7, 1, 4, 3 }} },
|
||||
{ "ldo8", 50000, 800000, 1050000, 2800000, REGULATOR_LDO, MAX77620_REG_LDO8_CFG, MAX77620_REG_LDO8_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO8, 3, 7, 0 }} },
|
||||
|
||||
{ "max77621_CPU", 6250, 606250, 1000000, 1400000, REGULATOR_BC0, MAX77621_VOUT_REG, MAX77621_VOUT_DVS_REG, MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} },
|
||||
{ "max77621_GPU", 6250, 606250, 1200000, 1400000, REGULATOR_BC0, MAX77621_VOUT_REG, MAX77621_VOUT_DVS_REG, MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} },
|
||||
{ "max77812_CPU", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M4_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M4_MASK, MAX77812_EN_CTRL_EN_M4_SHIFT, 0, 0 }} },
|
||||
//{ "max77812_GPU", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M1_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M1_MASK, MAX77812_EN_CTRL_EN_M1_SHIFT, 0, 0 }} },
|
||||
//{ "max77812_RAM", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M3_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M3_MASK, MAX77812_EN_CTRL_EN_M3_SHIFT, 0, 0 }} } // Only on PHASE211 configuration.
|
||||
};
|
||||
|
||||
static u8 _max77812_get_address()
|
||||
{
|
||||
static u8 max77812_i2c_addr = 0;
|
||||
|
||||
if (max77812_i2c_addr)
|
||||
return max77812_i2c_addr;
|
||||
|
||||
max77812_i2c_addr =
|
||||
!(FUSE(FUSE_RESERVED_ODM28_T210B01) & 1) ? MAX77812_PHASE31_CPU_I2C_ADDR : MAX77812_PHASE211_CPU_I2C_ADDR;
|
||||
|
||||
return max77812_i2c_addr;
|
||||
}
|
||||
|
||||
static u8 _max7762x_get_i2c_address(u32 id)
|
||||
{
|
||||
const max77620_regulator_t *reg = &_pmic_regulators[id];
|
||||
|
||||
// Choose the correct i2c address.
|
||||
switch (reg->type)
|
||||
{
|
||||
case REGULATOR_SD:
|
||||
case REGULATOR_LDO:
|
||||
return MAX77620_I2C_ADDR;
|
||||
case REGULATOR_BC0:
|
||||
return (id == REGULATOR_CPU0 ? MAX77621_CPU_I2C_ADDR : MAX77621_GPU_I2C_ADDR);
|
||||
case REGULATOR_BC1:
|
||||
return _max77812_get_address();
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
static void _max7762x_set_reg(u8 addr, u8 reg, u8 val)
|
||||
{
|
||||
u32 retries = 100;
|
||||
while (retries)
|
||||
{
|
||||
if (i2c_send_byte(I2C_5, addr, reg, val))
|
||||
break;
|
||||
|
||||
usleep(50);
|
||||
retries--;
|
||||
}
|
||||
}
|
||||
|
||||
int max77620_regulator_get_status(u32 id)
|
||||
{
|
||||
if (id > REGULATOR_LDO8)
|
||||
return 0;
|
||||
|
||||
const max77620_regulator_t *reg = &_pmic_regulators[id];
|
||||
|
||||
// SD power OK status.
|
||||
if (reg->type == REGULATOR_SD)
|
||||
{
|
||||
u8 mask = 1u << (7 - id);
|
||||
return (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_STATSD) & mask) ? 0 : 1;
|
||||
}
|
||||
|
||||
// LDO power OK status.
|
||||
return (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, reg->cfg_addr) & MAX77620_LDO_CFG2_POK_MASK) ? 1 : 0;
|
||||
}
|
||||
|
||||
int max77620_regulator_config_fps(u32 id)
|
||||
{
|
||||
if (id > REGULATOR_LDO8)
|
||||
return 0;
|
||||
|
||||
const max77620_regulator_t *reg = &_pmic_regulators[id];
|
||||
|
||||
// Set FPS configuration.
|
||||
_max7762x_set_reg(MAX77620_I2C_ADDR,
|
||||
reg->fps.fps_addr,
|
||||
(reg->fps.fps_src << MAX77620_FPS_SRC_SHIFT) |
|
||||
(reg->fps.pu_period << MAX77620_FPS_PU_PERIOD_SHIFT) |
|
||||
(reg->fps.pd_period << MAX77620_FPS_PD_PERIOD_SHIFT));
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int max7762x_regulator_set_voltage(u32 id, u32 mv)
|
||||
{
|
||||
if (id > REGULATOR_MAX)
|
||||
return 0;
|
||||
|
||||
const max77620_regulator_t *reg = &_pmic_regulators[id];
|
||||
|
||||
if (mv < reg->uv_min || mv > reg->uv_max)
|
||||
return 0;
|
||||
|
||||
u8 addr = _max7762x_get_i2c_address(id);
|
||||
|
||||
// Calculate voltage multiplier.
|
||||
u32 mult = (mv + reg->uv_step - 1 - reg->uv_min) / reg->uv_step;
|
||||
u8 val = i2c_recv_byte(I2C_5, addr, reg->volt_addr);
|
||||
val = (val & ~reg->volt_mask) | (mult & reg->volt_mask);
|
||||
|
||||
// Set voltage.
|
||||
_max7762x_set_reg(addr, reg->volt_addr, val);
|
||||
|
||||
// If max77621 set DVS voltage also.
|
||||
if (reg->type == REGULATOR_BC0)
|
||||
_max7762x_set_reg(addr, reg->cfg_addr, MAX77621_VOUT_ENABLE_MASK | val);
|
||||
|
||||
// Wait for ramp up/down delay.
|
||||
usleep(1000);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int max7762x_regulator_enable(u32 id, bool enable)
|
||||
{
|
||||
u8 reg_addr;
|
||||
u8 enable_val;
|
||||
u8 enable_mask;
|
||||
u8 enable_shift;
|
||||
|
||||
if (id > REGULATOR_MAX)
|
||||
return 0;
|
||||
|
||||
const max77620_regulator_t *reg = &_pmic_regulators[id];
|
||||
|
||||
// Choose the correct i2c and register addresses and mask/shift for each type.
|
||||
switch (reg->type)
|
||||
{
|
||||
case REGULATOR_SD:
|
||||
reg_addr = reg->cfg_addr;
|
||||
enable_val = MAX77620_POWER_MODE_NORMAL;
|
||||
enable_mask = MAX77620_SD_POWER_MODE_MASK;
|
||||
enable_shift = MAX77620_SD_POWER_MODE_SHIFT;
|
||||
break;
|
||||
case REGULATOR_LDO:
|
||||
reg_addr = reg->volt_addr;
|
||||
enable_val = MAX77620_POWER_MODE_NORMAL;
|
||||
enable_mask = MAX77620_LDO_POWER_MODE_MASK;
|
||||
enable_shift = MAX77620_LDO_POWER_MODE_SHIFT;
|
||||
break;
|
||||
case REGULATOR_BC0:
|
||||
reg_addr = reg->volt_addr;
|
||||
enable_val = MAX77621_VOUT_ENABLE;
|
||||
enable_mask = MAX77621_DVC_DVS_ENABLE_MASK;
|
||||
enable_shift = MAX77621_DVC_DVS_ENABLE_SHIFT;
|
||||
break;
|
||||
case REGULATOR_BC1:
|
||||
reg_addr = reg->cfg_addr;
|
||||
enable_val = MAX77812_EN_CTRL_ENABLE;
|
||||
enable_mask = reg->enable.mask;
|
||||
enable_shift = reg->enable.shift;
|
||||
break;
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
u8 addr = _max7762x_get_i2c_address(id);
|
||||
|
||||
// Read and enable/disable.
|
||||
u8 val = i2c_recv_byte(I2C_5, addr, reg_addr);
|
||||
val &= ~enable_mask;
|
||||
|
||||
if (enable)
|
||||
val |= (enable_val << enable_shift);
|
||||
|
||||
// Set enable.
|
||||
_max7762x_set_reg(addr, reg_addr, val);
|
||||
|
||||
// Wait for enable/disable ramp delay.
|
||||
usleep(1000);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
void max77620_config_gpio(u32 gpio_id, bool enable)
|
||||
{
|
||||
if (gpio_id > 7)
|
||||
return;
|
||||
|
||||
// Configure as standard GPIO.
|
||||
u8 val = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO);
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO, val & ~BIT(gpio_id));
|
||||
|
||||
// Set GPIO configuration.
|
||||
if (enable)
|
||||
val = MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH | MAX77620_CNFG_GPIO_DIR_OUTPUT | MAX77620_CNFG_GPIO_DRV_PUSHPULL;
|
||||
else
|
||||
val = MAX77620_CNFG_GPIO_DIR_INPUT | MAX77620_CNFG_GPIO_DRV_OPENDRAIN;
|
||||
i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO0 + gpio_id, val);
|
||||
}
|
||||
|
||||
void max77621_config_default(u32 id, bool por)
|
||||
{
|
||||
const max77620_regulator_t *reg = &_pmic_regulators[id];
|
||||
|
||||
if (reg->type != REGULATOR_BC0)
|
||||
return;
|
||||
|
||||
u8 addr = _max7762x_get_i2c_address(id);
|
||||
|
||||
if (por)
|
||||
{
|
||||
// Set voltage and disable power before changing the inductor.
|
||||
max7762x_regulator_set_voltage(id, 1000000);
|
||||
max7762x_regulator_enable(id, false);
|
||||
|
||||
// Configure to default.
|
||||
i2c_send_byte(I2C_5, addr, MAX77621_CONTROL1_REG, reg->ctrl.ctrl1_por);
|
||||
i2c_send_byte(I2C_5, addr, MAX77621_CONTROL2_REG, reg->ctrl.ctrl2_por);
|
||||
}
|
||||
else
|
||||
{
|
||||
i2c_send_byte(I2C_5, addr, MAX77621_CONTROL1_REG, reg->ctrl.ctrl1_hos);
|
||||
i2c_send_byte(I2C_5, addr, MAX77621_CONTROL2_REG, reg->ctrl.ctrl2_hos);
|
||||
}
|
||||
}
|
||||
|
||||
void max77620_config_default()
|
||||
{
|
||||
// Check if Erista OTP.
|
||||
if (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CID4) != 0x35)
|
||||
return;
|
||||
|
||||
// Set default voltages and enable regulators.
|
||||
for (u32 i = 1; i <= REGULATOR_LDO8; i++)
|
||||
{
|
||||
max77620_regulator_config_fps(i);
|
||||
max7762x_regulator_set_voltage(i, _pmic_regulators[i].uv_default);
|
||||
if (_pmic_regulators[i].fps.fps_src != MAX77620_FPS_SRC_NONE)
|
||||
max7762x_regulator_enable(i, true);
|
||||
}
|
||||
|
||||
// Enable SD0 output voltage sense and disable for SD1. Additionally disable the reserved bit.
|
||||
_max7762x_set_reg(MAX77620_I2C_ADDR, MAX77620_REG_SD_CFG2, MAX77620_SD_CNF2_ROVS_EN_SD0);
|
||||
}
|
||||
|
||||
// Stock HOS: disabled.
|
||||
void max77620_low_battery_monitor_config(bool enable)
|
||||
{
|
||||
_max7762x_set_reg(MAX77620_I2C_ADDR, MAX77620_REG_CNFGGLBL1,
|
||||
MAX77620_CNFGGLBL1_LBDAC_EN |
|
||||
(enable ? MAX77620_CNFGGLBL1_MPPLD : 0) |
|
||||
MAX77620_CNFGGLBL1_LBHYST_200 |
|
||||
MAX77620_CNFGGLBL1_LBDAC_2800);
|
||||
}
|
||||
148
bdk/power/max7762x.h
Normal file
148
bdk/power/max7762x.h
Normal file
|
|
@ -0,0 +1,148 @@
|
|||
/*
|
||||
* Copyright (c) 2018 naehrwert
|
||||
* Copyright (c) 2019-2020 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _MAX7762X_H_
|
||||
#define _MAX7762X_H_
|
||||
|
||||
#include <utils/types.h>
|
||||
|
||||
/*
|
||||
* Switch Power domains (max77620):
|
||||
* Name | Usage | uV step | uV min | uV default | uV max | Init
|
||||
*-------+---------------+---------+--------+------------+---------+------------------
|
||||
* sd0 | SoC | 12500 | 600000 | 625000 | 1400000 | 1.125V (pkg1.1)
|
||||
* sd1 | SDRAM | 12500 | 600000 | 1125000 | 1125000 | 1.1V (pkg1.1)
|
||||
* sd2 | ldo{0-1, 7-8} | 12500 | 600000 | 1325000 | 1350000 | 1.325V (pcv)
|
||||
* sd3 | 1.8V general | 12500 | 600000 | 1800000 | 1800000 |
|
||||
* ldo0 | Display Panel | 25000 | 800000 | 1200000 | 1200000 | 1.2V (pkg1.1)
|
||||
* ldo1 | XUSB, PCIE | 25000 | 800000 | 1050000 | 1050000 | 1.05V (pcv)
|
||||
* ldo2 | SDMMC1 | 50000 | 800000 | 1800000 | 3300000 |
|
||||
* ldo3 | GC ASIC | 50000 | 800000 | 3100000 | 3100000 | 3.1V (pcv)
|
||||
* ldo4 | RTC | 12500 | 800000 | 850000 | 850000 | 0.85V (AO, pcv)
|
||||
* ldo5 | GC Card | 50000 | 800000 | 1800000 | 1800000 | 1.8V (pcv)
|
||||
* ldo6 | Touch, ALS | 50000 | 800000 | 2900000 | 2900000 | 2.9V (pcv)
|
||||
* ldo7 | XUSB | 50000 | 800000 | 1050000 | 1050000 | 1.05V (pcv)
|
||||
* ldo8 | XUSB, DP, MCU | 50000 | 800000 | 1050000 | 2800000 | 1.05V/2.8V (pcv)
|
||||
*/
|
||||
|
||||
/*
|
||||
* MAX77620_AME_GPIO: control GPIO modes (bits 0 - 7 correspond to GPIO0 - GPIO7); 0 -> GPIO, 1 -> alt-mode
|
||||
* MAX77620_REG_GPIOx: 0x9 sets output and enable
|
||||
*/
|
||||
|
||||
/*! MAX77620 partitions. */
|
||||
#define REGULATOR_SD0 0
|
||||
#define REGULATOR_SD1 1
|
||||
#define REGULATOR_SD2 2
|
||||
#define REGULATOR_SD3 3
|
||||
#define REGULATOR_LDO0 4
|
||||
#define REGULATOR_LDO1 5
|
||||
#define REGULATOR_LDO2 6
|
||||
#define REGULATOR_LDO3 7
|
||||
#define REGULATOR_LDO4 8
|
||||
#define REGULATOR_LDO5 9
|
||||
#define REGULATOR_LDO6 10
|
||||
#define REGULATOR_LDO7 11
|
||||
#define REGULATOR_LDO8 12
|
||||
#define REGULATOR_CPU0 13
|
||||
#define REGULATOR_GPU0 14
|
||||
#define REGULATOR_CPU1 15
|
||||
//#define REGULATOR_GPU1 16
|
||||
//#define REGULATOR_GPU1 17
|
||||
#define REGULATOR_MAX 15
|
||||
|
||||
#define MAX77621_CPU_I2C_ADDR 0x1B
|
||||
#define MAX77621_GPU_I2C_ADDR 0x1C
|
||||
|
||||
#define MAX77621_VOUT_REG 0x00
|
||||
#define MAX77621_VOUT_DVS_REG 0x01
|
||||
#define MAX77621_CONTROL1_REG 0x02
|
||||
#define MAX77621_CONTROL2_REG 0x03
|
||||
#define MAX77621_CHIPID1_REG 0x04
|
||||
#define MAX77621_CHIPID2_REG 0x05
|
||||
|
||||
/* MAX77621_VOUT_DVC_DVS */
|
||||
#define MAX77621_DVC_DVS_VOLT_MASK 0x7F
|
||||
#define MAX77621_DVC_DVS_ENABLE_SHIFT 7
|
||||
#define MAX77621_DVC_DVS_ENABLE_MASK (1 << MAX77621_DVC_DVS_ENABLE_SHIFT)
|
||||
|
||||
/* MAX77621_VOUT */
|
||||
#define MAX77621_VOUT_DISABLE 0
|
||||
#define MAX77621_VOUT_ENABLE 1
|
||||
#define MAX77621_VOUT_ENABLE_MASK (MAX77621_VOUT_ENABLE << MAX77621_DVC_DVS_ENABLE_SHIFT)
|
||||
|
||||
/* MAX77621_CONTROL1 */
|
||||
#define MAX77621_RAMP_12mV_PER_US 0x0
|
||||
#define MAX77621_RAMP_25mV_PER_US 0x1
|
||||
#define MAX77621_RAMP_50mV_PER_US 0x2
|
||||
#define MAX77621_RAMP_200mV_PER_US 0x3
|
||||
#define MAX77621_RAMP_MASK 0x3
|
||||
|
||||
#define MAX77621_FREQSHIFT_9PER BIT(2)
|
||||
#define MAX77621_BIAS_ENABLE BIT(3)
|
||||
#define MAX77621_AD_ENABLE BIT(4)
|
||||
#define MAX77621_NFSR_ENABLE BIT(5)
|
||||
#define MAX77621_FPWM_EN_M BIT(6)
|
||||
#define MAX77621_SNS_ENABLE BIT(7)
|
||||
|
||||
/* MAX77621_CONTROL2 */
|
||||
#define MAX77621_INDUCTOR_MIN_30_PER 0
|
||||
#define MAX77621_INDUCTOR_NOMINAL 1
|
||||
#define MAX77621_INDUCTOR_PLUS_30_PER 2
|
||||
#define MAX77621_INDUCTOR_PLUS_60_PER 3
|
||||
#define MAX77621_INDUCTOR_MASK 3
|
||||
|
||||
#define MAX77621_CKKADV_TRIP_75mV_PER_US 0x0
|
||||
#define MAX77621_CKKADV_TRIP_150mV_PER_US BIT(2)
|
||||
#define MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS BIT(3)
|
||||
#define MAX77621_CKKADV_TRIP_DISABLE (BIT(2) | BIT(3))
|
||||
#define MAX77621_CKKADV_TRIP_MASK (BIT(2) | BIT(3))
|
||||
|
||||
#define MAX77621_FT_ENABLE BIT(4)
|
||||
#define MAX77621_DISCH_ENABLE BIT(5)
|
||||
#define MAX77621_WDTMR_ENABLE BIT(6)
|
||||
#define MAX77621_T_JUNCTION_120 BIT(7)
|
||||
|
||||
#define MAX77621_CPU_CTRL1_POR_DEFAULT (MAX77621_RAMP_50mV_PER_US)
|
||||
#define MAX77621_CPU_CTRL1_HOS_DEFAULT (MAX77621_AD_ENABLE | \
|
||||
MAX77621_NFSR_ENABLE | \
|
||||
MAX77621_SNS_ENABLE | \
|
||||
MAX77621_RAMP_12mV_PER_US)
|
||||
#define MAX77621_CPU_CTRL2_POR_DEFAULT (MAX77621_T_JUNCTION_120 | \
|
||||
MAX77621_FT_ENABLE | \
|
||||
MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS | \
|
||||
MAX77621_CKKADV_TRIP_150mV_PER_US | \
|
||||
MAX77621_INDUCTOR_NOMINAL)
|
||||
#define MAX77621_CPU_CTRL2_HOS_DEFAULT (MAX77621_T_JUNCTION_120 | \
|
||||
MAX77621_WDTMR_ENABLE | \
|
||||
MAX77621_CKKADV_TRIP_75mV_PER_US | \
|
||||
MAX77621_INDUCTOR_NOMINAL)
|
||||
|
||||
#define MAX77621_CTRL_HOS_CFG 0
|
||||
#define MAX77621_CTRL_POR_CFG 1
|
||||
|
||||
int max77620_regulator_get_status(u32 id);
|
||||
int max77620_regulator_config_fps(u32 id);
|
||||
int max7762x_regulator_set_voltage(u32 id, u32 mv);
|
||||
int max7762x_regulator_enable(u32 id, bool enable);
|
||||
void max77620_config_gpio(u32 id, bool enable);
|
||||
void max77620_config_default();
|
||||
void max77620_low_battery_monitor_config(bool enable);
|
||||
|
||||
void max77621_config_default(u32 id, bool por);
|
||||
|
||||
#endif
|
||||
105
bdk/power/max77812.h
Normal file
105
bdk/power/max77812.h
Normal file
|
|
@ -0,0 +1,105 @@
|
|||
/*
|
||||
* Copyright (c) 2020 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _MAX77812_H_
|
||||
#define _MAX77812_H_
|
||||
|
||||
#define MAX77812_PHASE31_CPU_I2C_ADDR 0x31 // 2 Outputs: 3-phase M1 + 1-phase M4.
|
||||
#define MAX77812_PHASE211_CPU_I2C_ADDR 0x33 // 3 Outputs: 2-phase M1 + 1-phase M3 + 1-phase M4.
|
||||
|
||||
#define MAX77812_REG_RSET 0x00
|
||||
#define MAX77812_REG_INT_SRC 0x01
|
||||
#define MAX77812_REG_INT_SRC_M 0x02
|
||||
#define MAX77812_REG_TOPSYS_INT 0x03
|
||||
#define MAX77812_REG_TOPSYS_INT_M 0x04
|
||||
#define MAX77812_REG_TOPSYS_STAT 0x05
|
||||
#define MAX77812_REG_EN_CTRL 0x06
|
||||
#define MAX77812_EN_CTRL_ENABLE 1
|
||||
#define MAX77812_EN_CTRL_EN_M1_SHIFT 0
|
||||
#define MAX77812_EN_CTRL_EN_M1_MASK (1 << MAX77812_EN_CTRL_EN_M1_SHIFT)
|
||||
#define MAX77812_EN_CTRL_EN_M2_SHIFT 2
|
||||
#define MAX77812_EN_CTRL_EN_M2_MASK (1 << MAX77812_EN_CTRL_EN_M2_SHIFT)
|
||||
#define MAX77812_EN_CTRL_EN_M3_SHIFT 4
|
||||
#define MAX77812_EN_CTRL_EN_M3_MASK (1 << MAX77812_EN_CTRL_EN_M3_SHIFT)
|
||||
#define MAX77812_EN_CTRL_EN_M4_SHIFT 6
|
||||
#define MAX77812_EN_CTRL_EN_M4_MASK (1 << MAX77812_EN_CTRL_EN_M4_SHIFT)
|
||||
#define MAX77812_REG_STUP_DLY2 0x07
|
||||
#define MAX77812_REG_STUP_DLY3 0x08
|
||||
#define MAX77812_REG_STUP_DLY4 0x09
|
||||
#define MAX77812_REG_SHDN_DLY1 0x0A
|
||||
#define MAX77812_REG_SHDN_DLY2 0x0B
|
||||
#define MAX77812_REG_SHDN_DLY3 0x0C
|
||||
#define MAX77812_REG_SHDN_DLY4 0x0D
|
||||
#define MAX77812_REG_WDTRSTB_DEB 0x0E
|
||||
#define MAX77812_REG_GPI_FUNC 0x0F
|
||||
#define MAX77812_REG_GPI_DEB1 0x10
|
||||
#define MAX77812_REG_GPI_DEB2 0x11
|
||||
#define MAX77812_REG_GPI_PD_CTRL 0x12
|
||||
#define MAX77812_REG_PROT_CFG 0x13
|
||||
#define MAX77812_REG_VERSION 0x14
|
||||
#define MAX77812_REG_I2C_CFG 0x15
|
||||
#define MAX77812_REG_BUCK_INT 0x20
|
||||
#define MAX77812_REG_BUCK_INT_M 0x21
|
||||
#define MAX77812_REG_BUCK_STAT 0x22
|
||||
#define MAX77812_REG_M1_VOUT 0x23 // GPU.
|
||||
#define MAX77812_REG_M2_VOUT 0x24
|
||||
#define MAX77812_REG_M3_VOUT 0x25 // DRAM on PHASE211.
|
||||
#define MAX77812_REG_M4_VOUT 0x26 // CPU.
|
||||
#define MAX77812_REG_M1_VOUT_D 0x27
|
||||
#define MAX77812_REG_M2_VOUT_D 0x28
|
||||
#define MAX77812_REG_M3_VOUT_D 0x29
|
||||
#define MAX77812_REG_M4_VOUT_D 0x2A
|
||||
#define MAX77812_REG_M1_VOUT_S 0x2B
|
||||
#define MAX77812_REG_M2_VOUT_S 0x2C
|
||||
#define MAX77812_REG_M3_VOUT_S 0x2D
|
||||
#define MAX77812_REG_M4_VOUT_S 0x2E
|
||||
#define MAX77812_REG_M1_CFG 0x2F
|
||||
#define MAX77812_REG_M2_CFG 0x30
|
||||
#define MAX77812_REG_M3_CFG 0x31
|
||||
#define MAX77812_REG_M4_CFG 0x32
|
||||
#define MAX77812_REG_GLB_CFG1 0x33
|
||||
#define MAX77812_REG_GLB_CFG2 0x34
|
||||
#define MAX77812_REG_GLB_CFG3 0x35
|
||||
|
||||
/*! Protected area and settings only for MAX77812_REG_VERSION 4 */
|
||||
#define MAX77812_REG_GLB_CFG4 0x36
|
||||
#define MAX77812_REG_GLB_CFG5 0x37
|
||||
#define MAX77812_REG_GLB_CFG6 0x38
|
||||
#define MAX77812_REG_GLB_CFG7 0x39
|
||||
#define MAX77812_REG_GLB_CFG8 0x3A
|
||||
#define MAX77812_REG_PROT_ACCESS 0xFD
|
||||
#define MAX77812_REG_MAX 0xFE
|
||||
|
||||
#define MAX77812_REG_EN_CTRL_MASK(n) BIT(n)
|
||||
#define MAX77812_START_SLEW_RATE_MASK 0x07
|
||||
#define MAX77812_SHDN_SLEW_RATE_MASK 0x70
|
||||
#define MAX77812_RAMPUP_SLEW_RATE_MASK 0x07
|
||||
#define MAX77812_RAMPDOWN_SLEW_RATE_MASK 0x70
|
||||
#define MAX77812_SLEW_RATE_SHIFT 4
|
||||
|
||||
#define MAX77812_OP_ACTIVE_DISCHARGE_MASK BIT(7)
|
||||
#define MAX77812_PEAK_CURRENT_LMT_MASK 0x70
|
||||
#define MAX77812_SWITCH_FREQ_MASK 0x0C
|
||||
#define MAX77812_FORCED_PWM_MASK BIT(1)
|
||||
#define MAX77812_SLEW_RATE_CNTRL_MASK BIT(0)
|
||||
#define MAX77812_START_SHD_DELAY_MASK 0x1F
|
||||
#define MAX77812_VERSION_MASK 0x07
|
||||
#define MAX77812_ES2_VERSION 0x04
|
||||
#define MAX77812_QS_VERSION 0x05
|
||||
|
||||
#define MAX77812_BUCK_VOLT_MASK 0xFF
|
||||
|
||||
#endif
|
||||
125
bdk/power/regulator_5v.c
Normal file
125
bdk/power/regulator_5v.c
Normal file
|
|
@ -0,0 +1,125 @@
|
|||
/*
|
||||
* Copyright (c) 2019-2021 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <soc/fuse.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/hw_init.h>
|
||||
#include <soc/pinmux.h>
|
||||
#include <soc/pmc.h>
|
||||
#include <soc/t210.h>
|
||||
#include <utils/types.h>
|
||||
|
||||
static u8 reg_5v_dev = 0;
|
||||
static bool usb_src = false;
|
||||
|
||||
void regulator_5v_enable(u8 dev)
|
||||
{
|
||||
// The power supply selection from battery or USB is automatic.
|
||||
if (!reg_5v_dev)
|
||||
{
|
||||
// Fan and Rail power from battery 5V regulator.
|
||||
PINMUX_AUX(PINMUX_AUX_SATA_LED_ACTIVE) = 1;
|
||||
gpio_config(GPIO_PORT_A, GPIO_PIN_5, GPIO_MODE_GPIO);
|
||||
gpio_output_enable(GPIO_PORT_A, GPIO_PIN_5, GPIO_OUTPUT_ENABLE);
|
||||
gpio_write(GPIO_PORT_A, GPIO_PIN_5, GPIO_HIGH);
|
||||
|
||||
// Only Icosa and Iowa have USB 5V VBUS rails. Skip on Hoag/Aula.
|
||||
u32 hw_type = fuse_read_hw_type();
|
||||
if (hw_type == FUSE_NX_HW_TYPE_ICOSA ||
|
||||
hw_type == FUSE_NX_HW_TYPE_IOWA)
|
||||
{
|
||||
// Fan and Rail power from USB 5V VBUS.
|
||||
PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN0) = PINMUX_LPDR | 1;
|
||||
gpio_config(GPIO_PORT_CC, GPIO_PIN_4, GPIO_MODE_GPIO);
|
||||
gpio_output_enable(GPIO_PORT_CC, GPIO_PIN_4, GPIO_OUTPUT_ENABLE);
|
||||
gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_LOW);
|
||||
}
|
||||
|
||||
// Enable GPIO AO IO rail for T210.
|
||||
if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210)
|
||||
{
|
||||
// Make sure GPIO power is enabled.
|
||||
PMC(APBDEV_PMC_NO_IOPOWER) &= ~PMC_NO_IOPOWER_GPIO_IO_EN;
|
||||
(void)PMC(APBDEV_PMC_NO_IOPOWER); // Commit write.
|
||||
|
||||
// Override power detect for GPIO AO IO rails.
|
||||
PMC(APBDEV_PMC_PWR_DET_VAL) &= ~PMC_PWR_DET_GPIO_IO_EN;
|
||||
(void)PMC(APBDEV_PMC_PWR_DET_VAL); // Commit write.
|
||||
}
|
||||
usb_src = false;
|
||||
}
|
||||
reg_5v_dev |= dev;
|
||||
}
|
||||
|
||||
void regulator_5v_disable(u8 dev)
|
||||
{
|
||||
reg_5v_dev &= ~dev;
|
||||
|
||||
if (!reg_5v_dev)
|
||||
{
|
||||
// Rail power from battery 5V regulator.
|
||||
gpio_write(GPIO_PORT_A, GPIO_PIN_5, GPIO_LOW);
|
||||
gpio_output_enable(GPIO_PORT_A, GPIO_PIN_5, GPIO_OUTPUT_DISABLE);
|
||||
gpio_config(GPIO_PORT_A, GPIO_PIN_5, GPIO_MODE_SPIO);
|
||||
PINMUX_AUX(PINMUX_AUX_SATA_LED_ACTIVE) = PINMUX_PARKED | PINMUX_INPUT_ENABLE;
|
||||
|
||||
// Only Icosa and Iowa have USB 5V VBUS rails. Skip on Hoag/Aula.
|
||||
u32 hw_type = fuse_read_hw_type();
|
||||
if (hw_type == FUSE_NX_HW_TYPE_ICOSA ||
|
||||
hw_type == FUSE_NX_HW_TYPE_IOWA)
|
||||
{
|
||||
// Rail power from USB 5V VBUS.
|
||||
gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_LOW);
|
||||
gpio_output_enable(GPIO_PORT_CC, GPIO_PIN_4, GPIO_OUTPUT_DISABLE);
|
||||
gpio_config(GPIO_PORT_CC, GPIO_PIN_4, GPIO_MODE_SPIO);
|
||||
PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN0) = PINMUX_IO_HV | PINMUX_LPDR | PINMUX_PARKED | PINMUX_INPUT_ENABLE;
|
||||
usb_src = false;
|
||||
|
||||
}
|
||||
|
||||
// GPIO AO IO rails.
|
||||
if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210)
|
||||
{
|
||||
PMC(APBDEV_PMC_PWR_DET_VAL) |= PMC_PWR_DET_GPIO_IO_EN;
|
||||
(void)PMC(APBDEV_PMC_PWR_DET_VAL); // Commit write.
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool regulator_5v_get_dev_enabled(u8 dev)
|
||||
{
|
||||
return (reg_5v_dev & dev);
|
||||
}
|
||||
|
||||
void regulator_5v_usb_src_enable(bool enable)
|
||||
{
|
||||
// Only for Icosa/Iowa. Skip on Hoag/Aula.
|
||||
u32 hw_type = fuse_read_hw_type();
|
||||
if (hw_type != FUSE_NX_HW_TYPE_ICOSA &&
|
||||
hw_type != FUSE_NX_HW_TYPE_IOWA)
|
||||
return;
|
||||
|
||||
if (enable && !usb_src)
|
||||
{
|
||||
gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_HIGH);
|
||||
usb_src = true;
|
||||
}
|
||||
else if (!enable && usb_src)
|
||||
{
|
||||
gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_LOW);
|
||||
usb_src = false;
|
||||
}
|
||||
}
|
||||
35
bdk/power/regulator_5v.h
Normal file
35
bdk/power/regulator_5v.h
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
/*
|
||||
* Copyright (c) 2019 CTCaer
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef _REGULATOR_5V_H_
|
||||
#define _REGULATOR_5V_H_
|
||||
|
||||
#include <utils/types.h>
|
||||
|
||||
enum
|
||||
{
|
||||
REGULATOR_5V_FAN = BIT(0),
|
||||
REGULATOR_5V_JC_R = BIT(1),
|
||||
REGULATOR_5V_JC_L = BIT(2),
|
||||
REGULATOR_5V_ALL = 0xFF
|
||||
};
|
||||
|
||||
void regulator_5v_enable(u8 dev);
|
||||
void regulator_5v_disable(u8 dev);
|
||||
bool regulator_5v_get_dev_enabled(u8 dev);
|
||||
void regulator_5v_usb_src_enable(bool enable);
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue