Add BPMP overclock, add hekate fixes, fix sprintf
This commit is contained in:
shchmue
parent
34890f0025
commit
82bea6be8f
39 changed files with 1130 additions and 544 deletions
112
source/gfx/di.c
112
source/gfx/di.c
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@ -18,15 +18,16 @@
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#include <string.h>
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#include "di.h"
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#include "../soc/t210.h"
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#include "../utils/util.h"
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#include "../soc/i2c.h"
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#include "../soc/pmc.h"
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#include "../gfx/gfx.h"
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#include "../power/max77620.h"
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#include "../power/max7762x.h"
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#include "../soc/gpio.h"
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#include "../soc/pinmux.h"
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#include "../soc/clock.h"
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#include "../soc/gpio.h"
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#include "../soc/i2c.h"
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#include "../soc/pinmux.h"
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#include "../soc/pmc.h"
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#include "../soc/t210.h"
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#include "../utils/util.h"
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#include "di.inl"
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@ -46,54 +47,61 @@ void display_init()
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max77620_regulator_set_volt_and_flags(REGULATOR_LDO0, 1200000, MAX77620_POWER_MODE_NORMAL); // Configure to 1.2V.
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i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO7, MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH | MAX77620_CNFG_GPIO_DRV_PUSHPULL);
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// Enable MIPI CAL, DSI, DISP1, HOST1X, UART_FST_MIPI_CAL, DSIA LP clocks.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = 0x1010000;
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = 0x1010000;
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = 0x18000000;
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = 0x18000000;
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = 0x20000;
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIP_CAL) = 0xA;
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_SET) = 0x80000;
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP) = 0xA;
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// Enable Display Interface specific clocks.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = 0x1010000; // Clear reset DSI, MIPI_CAL.
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = 0x1010000; // Set enable clock DSI, MIPI_CAL.
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// DPD idle.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = 0x18000000; // Clear reset DISP1, HOST1X.
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = 0x18000000; // Set enable clock DISP1, HOST1X.
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = 0x20000; // Set enable clock UART_FST_MIPI_CAL.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL) = 10; // Set PLLP_OUT3 and div 6 (17MHz).
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_SET) = 0x80000; // Set enable clock DSIA_LP.
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CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP) = 10; // Set PLLP_OUT and div 6 (68MHz).
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// Disable deap power down.
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PMC(APBDEV_PMC_IO_DPD_REQ) = 0x40000000;
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PMC(APBDEV_PMC_IO_DPD2_REQ) = 0x40000000;
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// Config pins.
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// Config LCD and Backlight pins.
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PINMUX_AUX(PINMUX_AUX_NFC_EN) &= ~PINMUX_TRISTATE;
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PINMUX_AUX(PINMUX_AUX_NFC_INT) &= ~PINMUX_TRISTATE;
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PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) &= ~PINMUX_TRISTATE;
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PINMUX_AUX(PINMUX_AUX_LCD_BL_EN) &= ~PINMUX_TRISTATE;
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PINMUX_AUX(PINMUX_AUX_LCD_RST) &= ~PINMUX_TRISTATE;
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gpio_config(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_MODE_GPIO); // Backlight +-5V.
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gpio_output_enable(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_OUTPUT_ENABLE); // Backlight +-5V.
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// Set Backlight +-5V pins mode and direction
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gpio_config(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_MODE_GPIO);
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gpio_output_enable(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_OUTPUT_ENABLE);
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// Enable Backlight power.
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gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_HIGH); // Backlight +5V enable.
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usleep(10000);
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gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_HIGH); // Backlight -5V enable.
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usleep(10000);
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gpio_config(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, GPIO_MODE_GPIO); // Backlight PWM, Enable, Reset.
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// Configure Backlight pins (PWM, EN, RST).
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gpio_config(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, GPIO_MODE_GPIO);
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gpio_output_enable(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, GPIO_OUTPUT_ENABLE);
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gpio_write(GPIO_PORT_V, GPIO_PIN_1, GPIO_HIGH); // Backlight Enable enable.
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gpio_write(GPIO_PORT_V, GPIO_PIN_1, GPIO_HIGH); // Enable Backlight EN.
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// Config display interface and display.
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// Power up supply regulator for display interface.
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MIPI_CAL(MIPI_CAL_MIPI_BIAS_PAD_CFG2) = 0;
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// Set DISP1 clock source and parrent clock.
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exec_cfg((u32 *)CLOCK_BASE, _display_config_1, 4);
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// Setup display communication interfaces.
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exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_2, 94);
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exec_cfg((u32 *)DSI_BASE, _display_config_3, 61);
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usleep(10000);
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gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_HIGH); // Backlight Reset enable.
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// Enable Backlight Reset.
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gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_HIGH);
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usleep(60000);
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// Setups DSI packet configuration and request display id.
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DSI(_DSIREG(DSI_BTA_TIMING)) = 0x50204;
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DSI(_DSIREG(DSI_WR_DATA)) = 0x337; // MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE
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DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST;
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@ -122,19 +130,22 @@ void display_init()
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usleep(20000);
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// Configure PLLD for DISP1.
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exec_cfg((u32 *)CLOCK_BASE, _display_config_6, 3);
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// Finalize DSI configuration.
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exec_cfg((u32 *)DSI_BASE, _display_config_5, 21);
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DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = 4;
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exec_cfg((u32 *)DSI_BASE, _display_config_7, 10);
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usleep(10000);
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// Calibrate display communication pads.
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exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_8, 6);
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exec_cfg((u32 *)DSI_BASE, _display_config_9, 4);
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exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_10, 16);
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usleep(10000);
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// Enable video display controller.
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exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_11, 113);
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}
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@ -142,11 +153,10 @@ void display_backlight_pwm_init()
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{
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clock_enable_pwm();
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PWM(PWM_CONTROLLER_PWM_CSR_0) = (1 << 31); // Enable PWM
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PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN; // Enable PWM and set it to 25KHz PFM.
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PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) >> 2) << 2 | 1; // PWM clock source.
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PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & 0xFFFFFFFC) | 1; // PWM clock source.
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gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight power mode.
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}
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void display_backlight(bool enable)
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@ -167,7 +177,7 @@ void display_backlight_brightness(u32 brightness, u32 step_delay)
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{
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for (u32 i = old_value; i < brightness + 1; i++)
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{
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PWM(PWM_CONTROLLER_PWM_CSR_0) = (1 << 31) | (i << 16); // Enable PWM
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PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN | (i << 16); // Enable PWM and set it to 25KHz PFM.
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usleep(step_delay);
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}
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}
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@ -175,7 +185,7 @@ void display_backlight_brightness(u32 brightness, u32 step_delay)
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{
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for (u32 i = old_value; i > brightness; i--)
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{
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PWM(PWM_CONTROLLER_PWM_CSR_0) = (1 << 31) | (i << 16); // Enable PWM
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PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN | (i << 16); // Enable PWM and set it to 25KHz PFM.
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usleep(step_delay);
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}
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}
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@ -191,13 +201,14 @@ void display_end()
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DSI(_DSIREG(DSI_WR_DATA)) = 0x2805; // MIPI_DCS_SET_DISPLAY_OFF
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DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = READ_MUX | WRITE_MUX;
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0;
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DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0; // Disable host cmd packet.
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// De-initialize video controller.
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exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_12, 17);
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exec_cfg((u32 *)DSI_BASE, _display_config_13, 16);
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usleep(10000);
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// De-initialize display panel.
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if (_display_ver == 0x10)
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exec_cfg((u32 *)DSI_BASE, _display_config_14, 22);
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@ -206,31 +217,31 @@ void display_end()
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usleep(50000);
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// Disable display and backlight pins.
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gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_LOW); //Backlight Reset disable.
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usleep(10000);
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gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_LOW); //Backlight -5V disable.
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usleep(10000);
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gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_LOW); //Backlight +5V disable.
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usleep(10000);
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// Disable clocks.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = 0x1010000;
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_CLR) = 0x1010000;
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = 0x18000000;
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = 0x18000000;
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// Disable Display Interface specific clocks.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = 0x1010000; // Set reset clock DSI, MIPI_CAL.
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_CLR) = 0x1010000; // Clear enable clock DSI, MIPI_CAL.
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CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = 0x18000000; // Set reset DISP1, HOST1X.
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CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = 0x18000000; // Clear enable DISP1, HOST1X.
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// Power down pads.
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DSI(_DSIREG(DSI_PAD_CONTROL_0)) = DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF);
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DSI(_DSIREG(DSI_POWER_CONTROL)) = 0;
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// Switch to automatic function mode.
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gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight PWM.
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PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & ~PINMUX_TRISTATE) | PINMUX_TRISTATE;
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PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) >> 2) << 2 | 1;
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PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & 0xFFFFFFFC)| 1;
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}
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void display_color_screen(u32 color)
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@ -243,7 +254,6 @@ void display_color_screen(u32 color)
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DISPLAY_A(_DIREG(DC_WIN_CD_WIN_OPTIONS)) = 0;
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DISPLAY_A(_DIREG(DC_DISP_BLEND_BACKGROUND_COLOR)) = color;
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DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = (DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE) | GENERAL_ACT_REQ;
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usleep(35000);
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display_backlight(true);
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@ -252,11 +262,11 @@ void display_color_screen(u32 color)
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u32 *display_init_framebuffer()
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{
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// Sanitize framebuffer area.
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memset((u32 *)0xC0000000, 0, 0x3C0000);
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// This configures the framebuffer @ 0xC0000000 with a resolution of 1280x720 (line stride 768).
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memset((u32 *)FB_ADDRESS, 0, 0x3C0000);
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// This configures the framebuffer @ IPL_FB_ADDRESS with a resolution of 1280x720 (line stride 720).
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exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer, 32);
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usleep(35000);
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return (u32 *)0xC0000000;
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return (u32 *)FB_ADDRESS;
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}
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@ -20,6 +20,8 @@
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#include "../utils/types.h"
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#define FB_ADDRESS 0xC0000000
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/*! Display registers. */
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#define _DIREG(reg) ((reg) * 4)
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@ -233,7 +235,7 @@
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#define UV_LINE_STRIDE(x) (((x) & 0xffff) << 16)
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#define DC_WIN_DV_CONTROL 0x70E
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// The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER).
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/*! The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER). */
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#define DC_WINBUF_START_ADDR 0x800
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#define DC_WINBUF_ADDR_H_OFFSET 0x806
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#define DC_WINBUF_ADDR_V_OFFSET 0x808
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@ -333,7 +335,7 @@
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#define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8)
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#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0)
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#define DSI_PAD_CONTROL_CD 0x4c
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#define DSI_PAD_CONTROL_CD 0x4C
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#define DSI_VIDEO_MODE_CONTROL 0x4E
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#define DSI_PAD_CONTROL_1 0x4F
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@ -122,7 +122,7 @@ static const cfg_op_t _display_config_2[94] = {
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{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
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{DC_WIN_WIN_OPTIONS, 0},
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{DC_DISP_DISP_WIN_OPTIONS, 0},
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{DC_CMD_DISPLAY_COMMAND, 0},
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{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_STOP},
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{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
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{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}
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};
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@ -405,7 +405,7 @@ static const cfg_op_t _display_config_11[113] = {
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{DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT},
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{DC_WIN_WIN_OPTIONS, 0},
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{DC_DISP_DISP_WIN_OPTIONS, 0},
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{DC_CMD_DISPLAY_COMMAND, 0},
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{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_STOP},
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{DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE},
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{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ},
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{DC_CMD_STATE_ACCESS, 0},
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@ -455,7 +455,7 @@ static const cfg_op_t _display_config_12[17] = {
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{DC_CMD_STATE_ACCESS, 0},
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{DC_CMD_INT_ENABLE, 0},
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{DC_CMD_CONT_SYNCPT_VSYNC, 0},
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{DC_CMD_DISPLAY_COMMAND, 0},
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{DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_STOP},
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{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
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{DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ},
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{DC_CMD_STATE_CONTROL, GENERAL_UPDATE},
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@ -548,7 +548,7 @@ static const cfg_op_t cfg_display_framebuffer[32] = {
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{DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(720 * 2) | LINE_STRIDE(720 * 4)}, //768*2x768*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements.
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{DC_WIN_BUFFER_CONTROL, 0},
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{DC_WINBUF_SURFACE_KIND, 0}, //Regular surface.
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{DC_WINBUF_START_ADDR, 0xC0000000}, //Framebuffer address.
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{DC_WINBUF_START_ADDR, FB_ADDRESS}, //Framebuffer address.
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{DC_WINBUF_ADDR_H_OFFSET, 0},
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{DC_WINBUF_ADDR_V_OFFSET, 0},
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{DC_WIN_WIN_OPTIONS, 0},
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@ -128,12 +128,12 @@ void gfx_init_ctxt(u32 *fb, u32 width, u32 height, u32 stride)
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void gfx_clear_grey(u8 color)
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{
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memset(gfx_ctxt.fb, color, 0x3C0000);
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memset(gfx_ctxt.fb, color, gfx_ctxt.width * gfx_ctxt.height * 4);
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}
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void gfx_clear_color(u32 color)
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{
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for (u32 i = 0; i < gfx_ctxt.height * gfx_ctxt.stride; i++)
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for (u32 i = 0; i < gfx_ctxt.width * gfx_ctxt.height; i++)
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gfx_ctxt.fb[i] = color;
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}
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