Transition to hekate bdk layout

bdk/soc/bpmp.c

@@ -0,0 +1,308 @@
+/*
+ * BPMP-Lite Cache/MMU and Frequency driver for Tegra X1
+ *
+ * Copyright (c) 2019-2020 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <soc/bpmp.h>
+#include <soc/clock.h>
+#include <soc/t210.h>
+#include <memory_map.h>
+#include <utils/util.h>
+
+#define BPMP_MMU_CACHE_LINE_SIZE        0x20
+
+#define BPMP_CACHE_CONFIG               0x0
+#define  CFG_ENABLE_CACHE               (1 << 0)
+#define  CFG_ENABLE_SKEW_ASSOC          (1 << 1)
+#define  CFG_DISABLE_RANDOM_ALLOC       (1 << 2)
+#define  CFG_FORCE_WRITE_THROUGH        (1 << 3)
+#define  CFG_NEVER_ALLOCATE             (1 << 6)
+#define  CFG_ENABLE_INTERRUPT           (1 << 7)
+#define  CFG_MMU_TAG_MODE(x)            (x << 8)
+#define   TAG_MODE_PARALLEL             0
+#define   TAG_MODE_TAG_FIRST            1
+#define   TAG_MODE_MMU_FIRST            2
+#define  CFG_DISABLE_WRITE_BUFFER       (1 << 10)
+#define  CFG_DISABLE_READ_BUFFER        (1 << 11)
+#define  CFG_ENABLE_HANG_DETECT         (1 << 12)
+#define  CFG_FULL_LINE_DIRTY            (1 << 13)
+#define  CFG_TAG_CHK_ABRT_ON_ERR        (1 << 14)
+#define  CFG_TAG_CHK_CLR_ERR            (1 << 15)
+#define  CFG_DISABLE_SAMELINE           (1 << 16)
+#define  CFG_OBS_BUS_EN                 (1 << 31)
+
+#define BPMP_CACHE_LOCK                 0x4
+#define  LOCK_LINE(x)                   (1 << x)
+
+#define BPMP_CACHE_SIZE                 0xC
+#define BPMP_CACHE_LFSR                 0x10
+
+#define BPMP_CACHE_TAG_STATUS           0x14
+#define  TAG_STATUS_TAG_CHECK_ERROR     (1 << 0)
+#define  TAG_STATUS_CONFLICT_ADDR_MASK  0xFFFFFFE0
+
+#define BPMP_CACHE_CLKEN_OVERRIDE       0x18
+#define  CLKEN_OVERRIDE_WR_MCCIF_CLKEN  (1 << 0)
+#define  CLKEN_OVERRIDE_RD_MCCIF_CLKEN  (1 << 1)
+
+#define BPMP_CACHE_MAINT_ADDR           0x20
+#define BPMP_CACHE_MAINT_DATA           0x24
+
+#define BPMP_CACHE_MAINT_REQ            0x28
+#define  MAINT_REQ_WAY_BITMAP(x)        ((x) << 8)
+
+#define BPMP_CACHE_INT_MASK             0x40
+#define BPMP_CACHE_INT_CLEAR            0x44
+#define BPMP_CACHE_INT_RAW_EVENT        0x48
+#define BPMP_CACHE_INT_STATUS           0x4C
+#define  INT_MAINT_DONE                 (1 << 0)
+#define  INT_MAINT_ERROR                (1 << 1)
+
+#define BPMP_CACHE_RB_CFG               0x80
+#define BPMP_CACHE_WB_CFG               0x84
+
+#define BPMP_CACHE_MMU_FALLBACK_ENTRY   0xA0
+#define BPMP_CACHE_MMU_SHADOW_COPY_MASK 0xA4
+
+#define BPMP_CACHE_MMU_CFG              0xAC
+#define  MMU_CFG_BLOCK_MAIN_ENTRY_WR    (1 << 0)
+#define  MMU_CFG_SEQ_EN                 (1 << 1)
+#define  MMU_CFG_TLB_EN                 (1 << 2)
+#define  MMU_CFG_SEG_CHECK_ALL_ENTRIES  (1 << 3)
+#define  MMU_CFG_ABORT_STORE_LAST       (1 << 4)
+#define  MMU_CFG_CLR_ABORT              (1 << 5)
+
+#define BPMP_CACHE_MMU_CMD              0xB0
+#define  MMU_CMD_NOP                    0
+#define  MMU_CMD_INIT                   1
+#define  MMU_CMD_COPY_SHADOW            2
+
+#define BPMP_CACHE_MMU_ABORT_STAT       0xB4
+#define  ABORT_STAT_UNIT_MASK           0x7
+#define  ABORT_STAT_UNIT_NONE           0
+#define  ABORT_STAT_UNIT_CACHE          1
+#define  ABORT_STAT_UNIT_SEQ            2
+#define  ABORT_STAT_UNIT_TLB            3
+#define  ABORT_STAT_UNIT_SEG            4
+#define  ABORT_STAT_UNIT_FALLBACK       5
+#define  ABORT_STAT_OVERLAP             (1 << 3)
+#define  ABORT_STAT_ENTRY               (0x1F << 4)
+#define  ABORT_STAT_TYPE_MASK           (3 << 16)
+#define  ABORT_STAT_TYPE_EXE            (0 << 16)
+#define  ABORT_STAT_TYPE_RD             (1 << 16)
+#define  ABORT_STAT_TYPE_WR             (2 << 16)
+#define  ABORT_STAT_SIZE                (3 << 18)
+#define  ABORT_STAT_SEQ                 (1 << 20)
+#define  ABORT_STAT_PROT                (1 << 21)
+
+#define BPMP_CACHE_MMU_ABORT_ADDR       0xB8
+#define BPMP_CACHE_MMU_ACTIVE_ENTRIES   0xBC
+
+#define BPMP_MMU_SHADOW_ENTRY_BASE      (BPMP_CACHE_BASE + 0x400)
+#define BPMP_MMU_MAIN_ENTRY_BASE        (BPMP_CACHE_BASE + 0x800)
+#define  MMU_EN_CACHED                  (1 << 0)
+#define  MMU_EN_EXEC                    (1 << 1)
+#define  MMU_EN_READ                    (1 << 2)
+#define  MMU_EN_WRITE                   (1 << 3)
+
+bpmp_mmu_entry_t mmu_entries[] =
+{
+	{ DRAM_START, 0xFFFFFFFF, MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC | MMU_EN_CACHED, true },
+	{ IRAM_BASE,  0x4003FFFF, MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC | MMU_EN_CACHED, true }
+};
+
+void bpmp_mmu_maintenance(u32 op, bool force)
+{
+	if (!force && !(BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) & CFG_ENABLE_CACHE))
+		return;
+
+	BPMP_CACHE_CTRL(BPMP_CACHE_INT_CLEAR) = INT_MAINT_DONE;
+
+	// This is a blocking operation.
+	BPMP_CACHE_CTRL(BPMP_CACHE_MAINT_REQ) = MAINT_REQ_WAY_BITMAP(0xF) | op;
+
+	while(!(BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT) & INT_MAINT_DONE))
+		;
+
+	BPMP_CACHE_CTRL(BPMP_CACHE_INT_CLEAR) = BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT);
+}
+
+void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply)
+{
+	if (idx > 31)
+		return;
+
+	volatile bpmp_mmu_entry_t *mmu_entry = (bpmp_mmu_entry_t *)(BPMP_MMU_SHADOW_ENTRY_BASE + sizeof(bpmp_mmu_entry_t) * idx);
+
+	if (entry->enable)
+	{
+		mmu_entry->start_addr = ALIGN(entry->start_addr, BPMP_MMU_CACHE_LINE_SIZE);
+		mmu_entry->end_addr = ALIGN_DOWN(entry->end_addr, BPMP_MMU_CACHE_LINE_SIZE);
+		mmu_entry->attr = entry->attr;
+
+		BPMP_CACHE_CTRL(BPMP_CACHE_MMU_SHADOW_COPY_MASK) |= (1 << idx);
+
+		if (apply)
+			BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_COPY_SHADOW;
+	}
+}
+
+void bpmp_mmu_enable()
+{
+	if (BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) & CFG_ENABLE_CACHE)
+		return;
+
+	// Init BPMP MMU.
+	BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_INIT;
+	BPMP_CACHE_CTRL(BPMP_CACHE_MMU_FALLBACK_ENTRY) = MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC; // RWX for non-defined regions.
+	BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CFG) = MMU_CFG_SEQ_EN | MMU_CFG_TLB_EN | MMU_CFG_ABORT_STORE_LAST;
+
+	// Init BPMP MMU entries.
+	BPMP_CACHE_CTRL(BPMP_CACHE_MMU_SHADOW_COPY_MASK) = 0;
+	for (u32 idx = 0; idx < (sizeof(mmu_entries) / sizeof(bpmp_mmu_entry_t)); idx++)
+		bpmp_mmu_set_entry(idx, &mmu_entries[idx], false);
+
+	BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_COPY_SHADOW;
+
+	// Invalidate cache.
+	bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY, true);
+
+	// Enable cache.
+	BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) = CFG_ENABLE_CACHE | CFG_FORCE_WRITE_THROUGH |
+		CFG_MMU_TAG_MODE(TAG_MODE_PARALLEL) | CFG_TAG_CHK_ABRT_ON_ERR;
+
+	// HW bug. Invalidate cache again.
+	bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY, false);
+}
+
+void bpmp_mmu_disable()
+{
+	if (!(BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) & CFG_ENABLE_CACHE))
+		return;
+
+	// Clean and invalidate cache.
+	bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false);
+
+	// Disable cache.
+	BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) = 0;
+}
+
+// APB clock affects RTC, PWM, MEMFETCH, APE, USB, SOR PWM,
+// I2C host, DC/DSI/DISP. UART gives extra stress.
+// 92: 100% success ratio. 93-94: 595-602MHz has 99% success ratio. 95: 608MHz less.
+const u8 pll_divn[] = {
+	0,   // BPMP_CLK_NORMAL:      408MHz  0% - 136MHz APB.
+	85,  // BPMP_CLK_HIGH_BOOST:  544MHz 33% - 136MHz APB.
+	90,  // BPMP_CLK_SUPER_BOOST: 576MHz 41% - 144MHz APB.
+	92   // BPMP_CLK_HYPER_BOOST: 589MHz 44% - 147MHz APB.
+	// Do not use for public releases!
+	//95   // BPMP_CLK_DEV_BOOST: 608MHz 49% - 152MHz APB.
+};
+
+bpmp_freq_t bpmp_clock_set = BPMP_CLK_NORMAL;
+
+void bpmp_clk_rate_get()
+{
+	bool clk_src_is_pllp = ((CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) >> 4) & 7) == 3;
+
+	if (clk_src_is_pllp)
+		bpmp_clock_set = BPMP_CLK_NORMAL;
+	else
+	{
+		bpmp_clock_set = BPMP_CLK_HIGH_BOOST;
+
+		u8 pll_divn_curr = (CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) >> 10) & 0xFF;
+		for (u32 i = 1; i < sizeof(pll_divn); i++)
+		{
+			if (pll_divn[i] == pll_divn_curr)
+			{
+				bpmp_clock_set = i;
+				break;
+			}
+		}
+	}
+}
+
+void bpmp_clk_rate_set(bpmp_freq_t fid)
+{
+	if (fid > (BPMP_CLK_MAX - 1))
+		fid = BPMP_CLK_MAX - 1;
+
+	if (bpmp_clock_set == fid)
+		return;
+
+	if (fid)
+	{
+		if (bpmp_clock_set)
+		{
+			// Restore to PLLP source during PLLC4 configuration.
+			CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // PLLP_OUT.
+			msleep(1); // Wait a bit for clock source change.
+		}
+
+		// Configure and enable PLLC.
+		clock_enable_pllc(pll_divn[fid]);
+
+		// Set SCLK / HCLK / PCLK.
+		CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 3; // PCLK = HCLK / (3 + 1). HCLK == SCLK.
+		CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003310; // PLLC_OUT1 for active and CLKM for idle.
+	}
+	else
+	{
+		CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003330; // PLLP_OUT for active and CLKM for idle.
+		msleep(1); // Wait a bit for clock source change.
+		CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // PCLK = HCLK / (2 + 1). HCLK == SCLK.
+
+		// Disable PLLC to save power.
+		clock_disable_pllc();
+	}
+	bpmp_clock_set = fid;
+}
+
+// The following functions halt BPMP to reduce power while sleeping.
+// They are not as accurate as RTC at big values but they guarantee time+ delay.
+void bpmp_usleep(u32 us)
+{
+	u32 delay;
+
+	// Each iteration takes 1us.
+	while (us)
+	{
+		delay = (us > HALT_COP_MAX_CNT) ? HALT_COP_MAX_CNT : us;
+		us -= delay;
+
+		FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_WAIT_EVENT | HALT_COP_USEC | delay;
+	}
+}
+
+void bpmp_msleep(u32 ms)
+{
+	u32 delay;
+
+	// Iteration time is variable. ~200 - 1000us.
+	while (ms)
+	{
+		delay = (ms > HALT_COP_MAX_CNT) ? HALT_COP_MAX_CNT : ms;
+		ms -= delay;
+
+		FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_WAIT_EVENT | HALT_COP_MSEC | delay;
+	}
+}
+
+void bpmp_halt()
+{
+	FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_WAIT_EVENT | HALT_COP_JTAG;
+}

bdk/soc/bpmp.h

@@ -0,0 +1,68 @@
+/*
+ * BPMP-Lite Cache/MMU and Frequency driver for Tegra X1
+ *
+ * Copyright (c) 2019-2020 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _BPMP_H_
+#define _BPMP_H_
+
+#include <utils/types.h>
+
+typedef enum
+{
+	BPMP_MMU_MAINT_NOP                =  0,
+	BPMP_MMU_MAINT_CLEAN_PHY          =  1,
+	BPMP_MMU_MAINT_INVALID_PHY        =  2,
+	BPMP_MMU_MAINT_CLEAN_INVALID_PHY  =  3,
+	BPMP_MMU_MAINT_CLEAN_LINE         =  9,
+	BPMP_MMU_MAINT_INVALID_LINE       = 10,
+	BPMP_MMU_MAINT_CLEAN_INVALID_LINE = 11,
+	BPMP_MMU_MAINT_CLEAN_WAY          = 17,
+	BPMP_MMU_MAINT_INVALID_WAY        = 18,
+	BPMP_MMU_MAINT_CLN_INV_WAY        = 19
+} bpmp_maintenance_t;
+
+typedef struct _bpmp_mmu_entry_t
+{
+	u32 start_addr;
+	u32 end_addr;
+	u32 attr;
+	u32 enable;
+} bpmp_mmu_entry_t;
+
+typedef enum
+{
+	BPMP_CLK_NORMAL,      // 408MHz  0% - 136MHz APB.
+	BPMP_CLK_HIGH_BOOST,  // 544MHz 33% - 136MHz APB.
+	BPMP_CLK_SUPER_BOOST, // 576MHz 41% - 144MHz APB.
+	BPMP_CLK_HYPER_BOOST, // 589MHz 44% - 147MHz APB.
+	//BPMP_CLK_DEV_BOOST, // 608MHz 49% - 152MHz APB.
+	BPMP_CLK_MAX
+} bpmp_freq_t;
+
+#define BPMP_CLK_DEFAULT_BOOST BPMP_CLK_HYPER_BOOST
+
+void bpmp_mmu_maintenance(u32 op, bool force);
+void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply);
+void bpmp_mmu_enable();
+void bpmp_mmu_disable();
+void bpmp_clk_rate_get();
+void bpmp_clk_rate_set(bpmp_freq_t fid);
+void bpmp_usleep(u32 us);
+void bpmp_msleep(u32 ms);
+void bpmp_halt();
+
+#endif

bdk/soc/ccplex.c

@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <soc/ccplex.h>
+#include <soc/i2c.h>
+#include <soc/clock.h>
+#include <utils/util.h>
+#include <soc/pmc.h>
+#include <soc/t210.h>
+#include <power/max77620.h>
+#include <power/max7762x.h>
+
+void _ccplex_enable_power()
+{
+	u8 tmp = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO); // Get current pinmuxing
+	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_AME_GPIO, tmp & ~(1 << 5)); // Disable GPIO5 pinmuxing.
+	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, MAX77620_CNFG_GPIO_DRV_PUSHPULL | MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH);
+
+	// Enable cores power.
+	// 1-3.x: MAX77621_NFSR_ENABLE.
+	i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL1_REG,
+		MAX77621_AD_ENABLE | MAX77621_NFSR_ENABLE | MAX77621_SNS_ENABLE | MAX77621_RAMP_12mV_PER_US);
+	// 1.0.0-3.x: MAX77621_T_JUNCTION_120 | MAX77621_CKKADV_TRIP_DISABLE | MAX77621_INDUCTOR_NOMINAL.
+	i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL2_REG,
+		MAX77621_T_JUNCTION_120 | MAX77621_WDTMR_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US| MAX77621_INDUCTOR_NOMINAL);
+	i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_0_95V);
+	i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_DVS_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_0_95V);
+}
+
+int _ccplex_pmc_enable_partition(u32 part, int enable)
+{
+	u32 part_mask = 1 << part;
+	u32 desired_state = enable << part;
+
+	// Check if the partition has the state we want.
+	if ((PMC(APBDEV_PMC_PWRGATE_STATUS) & part_mask) == desired_state)
+		return 1;
+
+	u32 i = 5001;
+	while (PMC(APBDEV_PMC_PWRGATE_TOGGLE) & 0x100)
+	{
+		usleep(1);
+		i--;
+		if (i < 1)
+			return 0;
+	}
+
+	// Toggle power gating.
+	PMC(APBDEV_PMC_PWRGATE_TOGGLE) = part | 0x100;
+
+	i = 5001;
+	while (i > 0)
+	{
+		if ((PMC(APBDEV_PMC_PWRGATE_STATUS) & part_mask) == desired_state)
+			break;
+		usleep(1);
+		i--;
+	}
+
+	return 1;
+}
+
+void ccplex_boot_cpu0(u32 entry)
+{
+	// Set ACTIVE_CLUSER to FAST.
+	FLOW_CTLR(FLOW_CTLR_BPMP_CLUSTER_CONTROL) &= 0xFFFFFFFE;
+
+	_ccplex_enable_power();
+
+	if (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x40000000)) // PLLX_ENABLE.
+	{
+		CLOCK(CLK_RST_CONTROLLER_PLLX_MISC_3) &= 0xFFFFFFF7; // Disable IDDQ.
+		usleep(2);
+		CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x80404E02;
+		CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x404E02;
+		CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) = (CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) & 0xFFFBFFFF) | 0x40000;
+		CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x40404E02;
+	}
+	while (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x8000000))
+		;
+
+	// Configure MSELECT source and enable clock.
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) & 0x1FFFFF00) | 6;
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) & 0xFFFFFFF7) | 8;
+
+	// Configure initial CPU clock frequency and enable clock.
+	CLOCK(CLK_RST_CONTROLLER_CCLK_BURST_POLICY) = 0x20008888;
+	CLOCK(CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER) = 0x80000000;
+	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = 1;
+
+	clock_enable_coresight();
+
+	// CAR2PMC_CPU_ACK_WIDTH should be set to 0.
+	CLOCK(CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2) &= 0xFFFFF000;
+
+	// Enable CPU rail.
+	_ccplex_pmc_enable_partition(0, 1);
+	// Enable cluster 0 non-CPU.
+	_ccplex_pmc_enable_partition(15, 1);
+	// Enable CE0.
+	_ccplex_pmc_enable_partition(14, 1);
+
+	// Request and wait for RAM repair.
+	FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) = 1;
+	while (!(FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) & 2))
+		;
+
+	EXCP_VEC(EVP_CPU_RESET_VECTOR) = 0;
+
+	// Set reset vector.
+	SB(SB_AA64_RESET_LOW) = entry | SB_AA64_RST_AARCH64_MODE_EN;
+	SB(SB_AA64_RESET_HIGH) = 0;
+	// Non-secure reset vector write disable.
+	SB(SB_CSR) = SB_CSR_NS_RST_VEC_WR_DIS;
+	(void)SB(SB_CSR);
+
+	// Tighten up the security aperture.
+	// MC(MC_TZ_SECURITY_CTRL) = 1;
+
+	// Clear MSELECT reset.
+	CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_V) &= 0xFFFFFFF7;
+	// Clear NONCPU reset.
+	CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x20000000;
+	// Clear CPU0 reset.
+	// < 5.x: 0x411F000F, Clear CPU{0,1,2,3} POR and CORE, CX0, L2, and DBG reset.
+	CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x41010001;
+}

bdk/soc/ccplex.h

@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _CCPLEX_H_
+#define _CCPLEX_H_
+
+#include <utils/types.h>
+
+void ccplex_boot_cpu0(u32 entry);
+
+#endif

bdk/soc/clock.c

@@ -0,0 +1,716 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018-2020 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <soc/clock.h>
+#include <soc/t210.h>
+#include <storage/sdmmc.h>
+#include <utils/util.h>
+
+/*
+ * CLOCK Peripherals:
+ * L   0 -  31
+ * H  32 -  63
+ * U  64 -  95
+ * V  96 - 127
+ * W 128 - 159
+ * X 160 - 191
+ * Y 192 - 223
+ */
+
+/* clock_t: reset, enable, source, index, clk_src, clk_div */
+
+static const clock_t _clock_uart[] = {
+/* UART A */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA,   6,  0, 2 },
+/* UART B */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB,   7,  0, 2 },
+/* UART C */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC,   23, 0, 2 },
+/* UART D */ { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_UARTD,   1,  0, 2 },
+/* UART E */ { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE, 20, 0, 2 }
+};
+
+//I2C default parameters - TLOW: 4, THIGH: 2, DEBOUNCE: 0, FM_DIV: 26.
+static const clock_t _clock_i2c[] = {
+/* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 12, 0, 19 }, //20.4MHz -> 100KHz
+/* I2C2 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C2, 22, 0, 4  }, //81.6MHz -> 400KHz
+/* I2C3 */ { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_I2C3, 3,  0, 4  }, //81.6MHz -> 400KHz
+/* I2C4 */ { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_I2C4, 7,  0, 19 }, //20.4MHz -> 100KHz
+/* I2C5 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 15, 0, 4  }, //81.6MHz -> 400KHz
+/* I2C6 */ { CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_I2C6, 6,  0, 19 }  //20.4MHz -> 100KHz
+};
+
+static clock_t _clock_se = {
+	CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE,     31, 0, 0
+};
+
+static clock_t _clock_tzram = {
+	CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_NO_SOURCE,                        30, 0, 0
+};
+
+static clock_t _clock_host1x = {
+	CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, 28, 4, 3
+};
+static clock_t _clock_tsec = {
+	CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC,   19, 0, 2
+};
+static clock_t _clock_sor_safe = {
+	CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_NO_SOURCE,                        30, 0, 0
+};
+static clock_t _clock_sor0 = {
+	CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_NO_SOURCE,                        22, 0, 0
+};
+static clock_t _clock_sor1 = {
+	CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1,   23, 0, 2
+};
+static clock_t _clock_kfuse = {
+	CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE,                        8,  0, 0
+};
+
+static clock_t _clock_cl_dvfs =	{
+	CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_NO_SOURCE,                        27, 0, 0
+};
+static clock_t _clock_coresight = {
+	CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE,   9, 0, 4
+};
+
+static clock_t _clock_pwm = {
+	CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM,    17, 6, 4 // Fref: 6.2MHz.
+};
+
+static clock_t _clock_sdmmc_legacy_tm = {
+	CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM, 1, 4, 66
+};
+
+void clock_enable(const clock_t *clk)
+{
+	// Put clock into reset.
+	CLOCK(clk->reset) = (CLOCK(clk->reset) & ~(1 << clk->index)) | (1 << clk->index);
+	// Disable.
+	CLOCK(clk->enable) &= ~(1 << clk->index);
+	// Configure clock source if required.
+	if (clk->source)
+		CLOCK(clk->source) = clk->clk_div | (clk->clk_src << 29);
+	// Enable.
+	CLOCK(clk->enable) = (CLOCK(clk->enable) & ~(1 << clk->index)) | (1 << clk->index);
+	usleep(2);
+
+	// Take clock off reset.
+	CLOCK(clk->reset) &= ~(1 << clk->index);
+}
+
+void clock_disable(const clock_t *clk)
+{
+	// Put clock into reset.
+	CLOCK(clk->reset) = (CLOCK(clk->reset) & ~(1 << clk->index)) | (1 << clk->index);
+	// Disable.
+	CLOCK(clk->enable) &= ~(1 << clk->index);
+}
+
+void clock_enable_fuse(bool enable)
+{
+	CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) = (CLOCK(CLK_RST_CONTROLLER_MISC_CLK_ENB) & 0xEFFFFFFF) | ((enable & 1) << 28);
+}
+
+void clock_enable_uart(u32 idx)
+{
+	clock_enable(&_clock_uart[idx]);
+}
+
+void clock_disable_uart(u32 idx)
+{
+	clock_disable(&_clock_uart[idx]);
+}
+
+#define UART_SRC_CLK_DIV_EN (1 << 24)
+
+int clock_uart_use_src_div(u32 idx, u32 baud)
+{
+	u32 clk_src_div = CLOCK(_clock_uart[idx].source) & 0xE0000000;
+
+	if (baud == 1000000)
+		CLOCK(_clock_uart[idx].source) = clk_src_div | UART_SRC_CLK_DIV_EN | 49;
+	else
+	{
+		CLOCK(_clock_uart[idx].source) = clk_src_div | 2;
+
+		return 1;
+	}
+
+	return 0;
+}
+
+void clock_enable_i2c(u32 idx)
+{
+	clock_enable(&_clock_i2c[idx]);
+}
+
+void clock_disable_i2c(u32 idx)
+{
+	clock_disable(&_clock_i2c[idx]);
+}
+
+void clock_enable_se()
+{
+	clock_enable(&_clock_se);
+}
+
+void clock_enable_tzram()
+{
+	clock_enable(&_clock_tzram);
+}
+
+void clock_enable_host1x()
+{
+	clock_enable(&_clock_host1x);
+}
+
+void clock_disable_host1x()
+{
+	clock_disable(&_clock_host1x);
+}
+
+void clock_enable_tsec()
+{
+	clock_enable(&_clock_tsec);
+}
+
+void clock_disable_tsec()
+{
+	clock_disable(&_clock_tsec);
+}
+
+void clock_enable_sor_safe()
+{
+	clock_enable(&_clock_sor_safe);
+}
+
+void clock_disable_sor_safe()
+{
+	clock_disable(&_clock_sor_safe);
+}
+
+void clock_enable_sor0()
+{
+	clock_enable(&_clock_sor0);
+}
+
+void clock_disable_sor0()
+{
+	clock_disable(&_clock_sor0);
+}
+
+void clock_enable_sor1()
+{
+	clock_enable(&_clock_sor1);
+}
+
+void clock_disable_sor1()
+{
+	clock_disable(&_clock_sor1);
+}
+
+void clock_enable_kfuse()
+{
+	//clock_enable(&_clock_kfuse);
+	CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) = (CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) & 0xFFFFFEFF) | 0x100;
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) &= 0xFFFFFEFF;
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) = (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) & 0xFFFFFEFF) | 0x100;
+	usleep(10);
+	CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_H) &= 0xFFFFFEFF;
+	usleep(20);
+}
+
+void clock_disable_kfuse()
+{
+	clock_disable(&_clock_kfuse);
+}
+
+void clock_enable_cl_dvfs()
+{
+	clock_enable(&_clock_cl_dvfs);
+}
+
+void clock_disable_cl_dvfs()
+{
+	clock_disable(&_clock_cl_dvfs);
+}
+
+void clock_enable_coresight()
+{
+	clock_enable(&_clock_coresight);
+}
+
+void clock_disable_coresight()
+{
+	clock_disable(&_clock_coresight);
+}
+
+void clock_enable_pwm()
+{
+	clock_enable(&_clock_pwm);
+}
+
+void clock_disable_pwm()
+{
+	clock_disable(&_clock_pwm);
+}
+
+void clock_enable_pllc(u32 divn)
+{
+	u8 pll_divn_curr = (CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) >> 10) & 0xFF;
+
+	// Check if already enabled and configured.
+	if ((CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) & PLLCX_BASE_ENABLE) && (pll_divn_curr == divn))
+		return;
+
+	// Take PLLC out of reset and set basic misc parameters.
+	CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) =
+		((CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) & 0xFFF0000F) & ~PLLC_MISC_RESET) | (0x80000 << 4); // PLLC_EXT_FRU.
+	CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_2) |= 0xF0 << 8; // PLLC_FLL_LD_MEM.
+
+	// Disable PLL and IDDQ in case they are on.
+	CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) &= ~PLLCX_BASE_ENABLE;
+	CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_1) &= ~PLLC_MISC1_IDDQ;
+	usleep(10);
+
+	// Set PLLC dividers.
+	CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) = (divn << 10) | 4; // DIVM: 4, DIVP: 1.
+
+	// Enable PLLC and wait for Phase and Frequency lock.
+	CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) |= PLLCX_BASE_ENABLE;
+	while (!(CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) & PLLCX_BASE_LOCK))
+		;
+
+	// Disable PLLC_OUT1, enable reset and set div to 1.5.
+	CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) = (1 << 8);
+
+	// Enable PLLC_OUT1 and bring it out of reset.
+	CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) |= (PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
+	msleep(1); // Wait a bit for PLL to stabilize.
+}
+
+void clock_disable_pllc()
+{
+	// Disable PLLC and PLLC_OUT1.
+	CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) &= ~(PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR);
+	CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) &= ~PLLCX_BASE_ENABLE;
+	CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) |= PLLCX_BASE_REF_DIS;
+	CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_1) |= PLLC_MISC1_IDDQ;
+	CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) |= PLLC_MISC_RESET;
+	usleep(10);
+}
+
+#define PLLC4_ENABLED (1 << 31)
+#define PLLC4_IN_USE  (~PLLC4_ENABLED)
+
+u32 pllc4_enabled = 0;
+
+static void _clock_enable_pllc4(u32 mask)
+{
+	pllc4_enabled |= mask;
+
+	if (pllc4_enabled & PLLC4_ENABLED)
+		return;
+
+	// Enable Phase and Frequency lock detection.
+	//CLOCK(CLK_RST_CONTROLLER_PLLC4_MISC) = PLLC4_MISC_EN_LCKDET;
+
+	// Disable PLL and IDDQ in case they are on.
+	CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) &= ~PLLCX_BASE_ENABLE;
+	CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) &= ~PLLC4_BASE_IDDQ;
+	usleep(10);
+
+	// Set PLLC4 dividers.
+	CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) = (104 << 8) | 4; // DIVM: 4, DIVP: 1.
+
+	// Enable PLLC4 and wait for Phase and Frequency lock.
+	CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) |= PLLCX_BASE_ENABLE;
+	while (!(CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) & PLLCX_BASE_LOCK))
+		;
+
+	msleep(1); // Wait a bit for PLL to stabilize.
+
+	pllc4_enabled |= PLLC4_ENABLED;
+}
+
+static void _clock_disable_pllc4(u32 mask)
+{
+	pllc4_enabled &= ~mask;
+
+	// Check if currently in use or disabled.
+	if ((pllc4_enabled & PLLC4_IN_USE) || !(pllc4_enabled & PLLC4_ENABLED))
+		return;
+
+	// Disable PLLC4.
+	msleep(1); // Wait at least 1ms to prevent glitching.
+	CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) &= ~PLLCX_BASE_ENABLE;
+	CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) |= PLLC4_BASE_IDDQ;
+	usleep(10);
+
+	pllc4_enabled = 0;
+}
+
+#define L_SWR_SDMMC1_RST (1 << 14)
+#define L_SWR_SDMMC2_RST (1 << 9)
+#define L_SWR_SDMMC4_RST (1 << 15)
+#define U_SWR_SDMMC3_RST (1 << 5)
+
+#define L_CLK_ENB_SDMMC1 (1 << 14)
+#define L_CLK_ENB_SDMMC2 (1 << 9)
+#define L_CLK_ENB_SDMMC4 (1 << 15)
+#define U_CLK_ENB_SDMMC3 (1 << 5)
+
+#define L_SET_SDMMC1_RST (1 << 14)
+#define L_SET_SDMMC2_RST (1 << 9)
+#define L_SET_SDMMC4_RST (1 << 15)
+#define U_SET_SDMMC3_RST (1 << 5)
+
+#define L_CLR_SDMMC1_RST (1 << 14)
+#define L_CLR_SDMMC2_RST (1 << 9)
+#define L_CLR_SDMMC4_RST (1 << 15)
+#define U_CLR_SDMMC3_RST (1 << 5)
+
+#define L_SET_CLK_ENB_SDMMC1 (1 << 14)
+#define L_SET_CLK_ENB_SDMMC2 (1 << 9)
+#define L_SET_CLK_ENB_SDMMC4 (1 << 15)
+#define U_SET_CLK_ENB_SDMMC3 (1 << 5)
+
+#define L_CLR_CLK_ENB_SDMMC1 (1 << 14)
+#define L_CLR_CLK_ENB_SDMMC2 (1 << 9)
+#define L_CLR_CLK_ENB_SDMMC4 (1 << 15)
+#define U_CLR_CLK_ENB_SDMMC3 (1 << 5)
+
+static int _clock_sdmmc_is_reset(u32 id)
+{
+	switch (id)
+	{
+	case SDMMC_1:
+		return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & L_SWR_SDMMC1_RST;
+	case SDMMC_2:
+		return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & L_SWR_SDMMC2_RST;
+	case SDMMC_3:
+		return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_U) & U_SWR_SDMMC3_RST;
+	case SDMMC_4:
+		return CLOCK(CLK_RST_CONTROLLER_RST_DEVICES_L) & L_SWR_SDMMC4_RST;
+	}
+	return 0;
+}
+
+static void _clock_sdmmc_set_reset(u32 id)
+{
+	switch (id)
+	{
+	case SDMMC_1:
+		CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = L_SET_SDMMC1_RST;
+		break;
+	case SDMMC_2:
+		CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = L_SET_SDMMC2_RST;
+		break;
+	case SDMMC_3:
+		CLOCK(CLK_RST_CONTROLLER_RST_DEV_U_SET) = U_SET_SDMMC3_RST;
+		break;
+	case SDMMC_4:
+		CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = L_SET_SDMMC4_RST;
+		break;
+	}
+}
+
+static void _clock_sdmmc_clear_reset(u32 id)
+{
+	switch (id)
+	{
+	case SDMMC_1:
+		CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = L_CLR_SDMMC1_RST;
+		break;
+	case SDMMC_2:
+		CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = L_CLR_SDMMC2_RST;
+		break;
+	case SDMMC_3:
+		CLOCK(CLK_RST_CONTROLLER_RST_DEV_U_CLR) = U_CLR_SDMMC3_RST;
+		break;
+	case SDMMC_4:
+		CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = L_CLR_SDMMC4_RST;
+		break;
+	}
+}
+
+static int _clock_sdmmc_is_enabled(u32 id)
+{
+	switch (id)
+	{
+	case SDMMC_1:
+		return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & L_CLK_ENB_SDMMC1;
+	case SDMMC_2:
+		return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & L_CLK_ENB_SDMMC2;
+	case SDMMC_3:
+		return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_U) & U_CLK_ENB_SDMMC3;
+	case SDMMC_4:
+		return CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & L_CLK_ENB_SDMMC4;
+	}
+	return 0;
+}
+
+static void _clock_sdmmc_set_enable(u32 id)
+{
+	switch (id)
+	{
+	case SDMMC_1:
+		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = L_SET_CLK_ENB_SDMMC1;
+		break;
+	case SDMMC_2:
+		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = L_SET_CLK_ENB_SDMMC2;
+		break;
+	case SDMMC_3:
+		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_U_SET) = U_SET_CLK_ENB_SDMMC3;
+		break;
+	case SDMMC_4:
+		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = L_SET_CLK_ENB_SDMMC4;
+		break;
+	}
+}
+
+static void _clock_sdmmc_clear_enable(u32 id)
+{
+	switch (id)
+	{
+	case SDMMC_1:
+		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = L_CLR_CLK_ENB_SDMMC1;
+		break;
+	case SDMMC_2:
+		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = L_CLR_CLK_ENB_SDMMC2;
+		break;
+	case SDMMC_3:
+		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_U_CLR) = U_CLR_CLK_ENB_SDMMC3;
+		break;
+	case SDMMC_4:
+		CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = L_CLR_CLK_ENB_SDMMC4;
+		break;
+	}
+}
+
+static void _clock_sdmmc_config_legacy_tm()
+{
+	clock_t *clk = &_clock_sdmmc_legacy_tm;
+	if (!(CLOCK(clk->enable) & (1 << clk->index)))
+		clock_enable(clk);
+}
+
+typedef struct _clock_sdmmc_t
+{
+	u32 clock;
+	u32 real_clock;
+} clock_sdmmc_t;
+
+static clock_sdmmc_t _clock_sdmmc_table[4] = { 0 };
+
+#define SDMMC_CLOCK_SRC_PLLP_OUT0      0x0
+#define SDMMC_CLOCK_SRC_PLLC4_OUT2     0x3
+#define SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ 0x1
+
+static int _clock_sdmmc_config_clock_host(u32 *pclock, u32 id, u32 val)
+{
+	u32 divisor = 0;
+	u32 source = SDMMC_CLOCK_SRC_PLLP_OUT0;
+
+	if (id > SDMMC_4)
+		return 0;
+
+	// Get IO clock divisor.
+	switch (val)
+	{
+	case 25000:
+		*pclock = 24728;
+		divisor = 31; // 16.5 div.
+		break;
+	case 26000:
+		*pclock = 25500;
+		divisor = 30; // 16 div.
+		break;
+	case 40800:
+		*pclock = 40800;
+		divisor = 18; // 10 div.
+		break;
+	case 50000:
+		*pclock = 48000;
+		divisor = 15; // 8.5 div.
+		break;
+	case 52000:
+		*pclock = 51000;
+		divisor = 14; // 8 div.
+		break;
+	case 100000:
+		source = SDMMC_CLOCK_SRC_PLLC4_OUT2;
+		*pclock = 99840;
+		divisor = 2;  // 2 div.
+		break;
+	case 164000:
+		*pclock = 163200;
+		divisor = 3;  // 2.5 div.
+		break;
+	case 200000: // 240MHz evo+.
+		switch (id)
+		{
+		case SDMMC_1:
+			source = SDMMC_CLOCK_SRC_PLLC4_OUT2;
+			break;
+		case SDMMC_2:
+			source = SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ;
+			break;
+		case SDMMC_3:
+			source = SDMMC_CLOCK_SRC_PLLC4_OUT2;
+			break;
+		case SDMMC_4:
+			source = SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ;
+			break;
+		}
+		*pclock = 199680;
+		divisor = 0;  // 1 div.
+		break;
+	default:
+		*pclock = 24728;
+		divisor = 31; // 16.5 div.
+	}
+
+	_clock_sdmmc_table[id].clock = val;
+	_clock_sdmmc_table[id].real_clock = *pclock;
+
+	// Enable PLLC4 if in use by any SDMMC.
+	if (source)
+		_clock_enable_pllc4(1 << id);
+
+	// Set SDMMC legacy timeout clock.
+	_clock_sdmmc_config_legacy_tm();
+
+	// Set SDMMC clock.
+	switch (id)
+	{
+	case SDMMC_1:
+		CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1) = (source << 29) | divisor;
+		break;
+	case SDMMC_2:
+		CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2) = (source << 29) | divisor;
+		break;
+	case SDMMC_3:
+		CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3) = (source << 29) | divisor;
+		break;
+	case SDMMC_4:
+		CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4) = (source << 29) | divisor;
+		break;
+	}
+
+	return 1;
+}
+
+void clock_sdmmc_config_clock_source(u32 *pclock, u32 id, u32 val)
+{
+	if (_clock_sdmmc_table[id].clock == val)
+	{
+		*pclock = _clock_sdmmc_table[id].real_clock;
+	}
+	else
+	{
+		int is_enabled = _clock_sdmmc_is_enabled(id);
+		if (is_enabled)
+			_clock_sdmmc_clear_enable(id);
+		_clock_sdmmc_config_clock_host(pclock, id, val);
+		if (is_enabled)
+			_clock_sdmmc_set_enable(id);
+		_clock_sdmmc_is_reset(id);
+	}
+}
+
+void clock_sdmmc_get_card_clock_div(u32 *pclock, u16 *pdivisor, u32 type)
+{
+	// Get Card clock divisor.
+	switch (type)
+	{
+	case SDHCI_TIMING_MMC_ID: // Actual IO Freq: 380.59 KHz.
+		*pclock = 26000;
+		*pdivisor = 66;
+		break;
+	case SDHCI_TIMING_MMC_LS26:
+		*pclock = 26000;
+		*pdivisor = 1;
+		break;
+	case SDHCI_TIMING_MMC_HS52:
+		*pclock = 52000;
+		*pdivisor = 1;
+		break;
+	case SDHCI_TIMING_MMC_HS200:
+	case SDHCI_TIMING_MMC_HS400:
+	case SDHCI_TIMING_UHS_SDR104:
+		*pclock = 200000;
+		*pdivisor = 1;
+		break;
+	case SDHCI_TIMING_SD_ID: // Actual IO Freq: 380.43 KHz.
+		*pclock = 25000;
+		*pdivisor = 64;
+		break;
+	case SDHCI_TIMING_SD_DS12:
+	case SDHCI_TIMING_UHS_SDR12:
+		*pclock = 25000;
+		*pdivisor = 1;
+		break;
+	case SDHCI_TIMING_SD_HS25:
+	case SDHCI_TIMING_UHS_SDR25:
+		*pclock = 50000;
+		*pdivisor = 1;
+		break;
+	case SDHCI_TIMING_UHS_SDR50:
+		*pclock = 100000;
+		*pdivisor = 1;
+		break;
+	case SDHCI_TIMING_UHS_SDR82:
+		*pclock = 164000;
+		*pdivisor = 1;
+		break;
+	case SDHCI_TIMING_UHS_DDR50:
+		*pclock = 40800;
+		*pdivisor = 1;
+		break;
+	case SDHCI_TIMING_MMC_DDR52: // Actual IO Freq: 49.92 MHz.
+		*pclock = 200000;
+		*pdivisor = 2;
+		break;
+	}
+}
+
+int clock_sdmmc_is_not_reset_and_enabled(u32 id)
+{
+	return !_clock_sdmmc_is_reset(id) && _clock_sdmmc_is_enabled(id);
+}
+
+void clock_sdmmc_enable(u32 id, u32 val)
+{
+	u32 clock = 0;
+
+	if (_clock_sdmmc_is_enabled(id))
+		_clock_sdmmc_clear_enable(id);
+	_clock_sdmmc_set_reset(id);
+	_clock_sdmmc_config_clock_host(&clock, id, val);
+	_clock_sdmmc_set_enable(id);
+	_clock_sdmmc_is_reset(id);
+	usleep((100000 + clock - 1) / clock);
+	_clock_sdmmc_clear_reset(id);
+	_clock_sdmmc_is_reset(id);
+}
+
+void clock_sdmmc_disable(u32 id)
+{
+	_clock_sdmmc_set_reset(id);
+	_clock_sdmmc_clear_enable(id);
+	_clock_sdmmc_is_reset(id);
+	_clock_disable_pllc4(1 << id);
+}

bdk/soc/clock.h

@@ -0,0 +1,224 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018-2020 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _CLOCK_H_
+#define _CLOCK_H_
+
+#include <utils/types.h>
+
+/*! Clock registers. */
+#define CLK_RST_CONTROLLER_RST_SOURCE 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L 0x4
+#define CLK_RST_CONTROLLER_RST_DEVICES_H 0x8
+#define CLK_RST_CONTROLLER_RST_DEVICES_U 0xC
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L 0x10
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H 0x14
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U 0x18
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY 0x20
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER 0x24
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY 0x28
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER 0x2C
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB 0x48
+#define CLK_RST_CONTROLLER_OSC_CTRL 0x50
+#define CLK_RST_CONTROLLER_PLLC_BASE 0x80
+#define CLK_RST_CONTROLLER_PLLC_OUT 0x84
+#define CLK_RST_CONTROLLER_PLLC_MISC 0x88
+#define CLK_RST_CONTROLLER_PLLC_MISC_1 0x8C
+#define CLK_RST_CONTROLLER_PLLM_BASE 0x90
+#define CLK_RST_CONTROLLER_PLLM_MISC1 0x98
+#define CLK_RST_CONTROLLER_PLLM_MISC2 0x9C
+#define CLK_RST_CONTROLLER_PLLP_BASE 0xA0
+#define CLK_RST_CONTROLLER_PLLA_BASE 0xB0
+#define CLK_RST_CONTROLLER_PLLA_OUT 0xB4
+#define CLK_RST_CONTROLLER_PLLA_MISC1 0xB8
+#define CLK_RST_CONTROLLER_PLLA_MISC 0xBC
+#define CLK_RST_CONTROLLER_PLLU_BASE 0xC0
+#define CLK_RST_CONTROLLER_PLLU_MISC 0xCC
+#define CLK_RST_CONTROLLER_PLLD_BASE 0xD0
+#define CLK_RST_CONTROLLER_PLLD_MISC1 0xD8
+#define CLK_RST_CONTROLLER_PLLD_MISC 0xDC
+#define CLK_RST_CONTROLLER_PLLX_BASE 0xE0
+#define CLK_RST_CONTROLLER_PLLX_MISC 0xE4
+#define CLK_RST_CONTROLLER_PLLE_BASE 0xE8
+#define CLK_RST_CONTROLLER_PLLE_MISC 0xEC
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA 0xF8
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB 0xFC
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 0x100
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM 0x110
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 0x124
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 0x128
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1 0x138
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI 0x148
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 0x150
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 0x154
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 0x164
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA 0x178
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB 0x17C
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X 0x180
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 0x198
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC 0x1A0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 0x1B8
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 0x1BC
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD 0x1C0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE 0x1D4
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 0x1D8
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC 0x1F4
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X 0x280
+#define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x284
+#define CLK_RST_CONTROLLER_CLK_ENB_X_CLR 0x288
+#define CLK_RST_CONTROLLER_RST_DEVICES_X 0x28C
+#define CLK_RST_CONTROLLER_RST_DEV_X_SET 0x290
+#define CLK_RST_CONTROLLER_RST_DEV_X_CLR 0x294
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_Y 0x298
+#define CLK_RST_CONTROLLER_CLK_ENB_Y_SET 0x29C
+#define CLK_RST_CONTROLLER_CLK_ENB_Y_CLR 0x2A0
+#define CLK_RST_CONTROLLER_RST_DEVICES_Y 0x2A4
+#define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2A8
+#define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2AC
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET 0x300
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR 0x304
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET 0x308
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR 0x30C
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET 0x310
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR 0x314
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET 0x320
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR 0x324
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET 0x328
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR 0x32C
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET 0x330
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR 0x334
+#define CLK_RST_CONTROLLER_RST_DEVICES_V 0x358
+#define CLK_RST_CONTROLLER_RST_DEVICES_W 0x35C
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_V 0x360
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_W 0x364
+#define CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2 0x388
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC 0x3A0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD 0x3A4
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT 0x3B4
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 0x3C4
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 0x3EC
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SYS 0x400
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SE 0x42C
+#define CLK_RST_CONTROLLER_RST_DEV_V_SET 0x430
+#define CLK_RST_CONTROLLER_RST_DEV_V_CLR 0x434
+#define CLK_RST_CONTROLLER_RST_DEV_W_SET 0x438
+#define CLK_RST_CONTROLLER_RST_DEV_W_CLR 0x43C
+#define CLK_RST_CONTROLLER_CLK_ENB_V_SET 0x440
+#define CLK_RST_CONTROLLER_CLK_ENB_V_CLR 0x444
+#define CLK_RST_CONTROLLER_CLK_ENB_W_SET 0x448
+#define CLK_RST_CONTROLLER_CLK_ENB_W_CLR 0x44C
+#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET 0x450
+#define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR 0x454
+#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG0 0x480
+#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG1 0x484
+#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2 0x488
+#define CLK_RST_CONTROLLER_PLLE_AUX 0x48C
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S0 0x4A0
+#define CLK_RST_CONTROLLER_PLLX_MISC_3 0x518
+#define CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0 0x52C
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE 0x554
+#define CLK_RST_CONTROLLER_SPARE_REG0 0x55C
+#define CLK_RST_CONTROLLER_PLLC4_BASE 0x5A4
+#define CLK_RST_CONTROLLER_PLLC4_MISC 0x5A8
+#define CLK_RST_CONTROLLER_PLLC_MISC_2 0x5D0
+#define CLK_RST_CONTROLLER_PLLC4_OUT 0x5E4
+#define CLK_RST_CONTROLLER_PLLMB_BASE 0x5E8
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP 0x620
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 0x65C
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL 0x664
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL 0x66C
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM 0x694
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC 0x6A0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK 0x6CC
+#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER 0x704
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE 0x710
+
+#define CLK_NO_SOURCE 0x0
+
+/*! PLL control and status bits */
+#define PLLCX_BASE_ENABLE    (1 << 30)
+#define PLLCX_BASE_REF_DIS   (1 << 29)
+#define PLLCX_BASE_LOCK      (1 << 27)
+
+#define PLLA_BASE_IDDQ       (1 << 25)
+#define PLLA_OUT0_CLKEN      (1 << 1)
+#define PLLA_OUT0_RSTN_CLR   (1 << 0)
+
+#define PLLC_MISC_RESET      (1 << 30)
+#define PLLC_MISC1_IDDQ      (1 << 27)
+#define PLLC_OUT1_CLKEN      (1 << 1)
+#define PLLC_OUT1_RSTN_CLR   (1 << 0)
+
+#define PLLC4_MISC_EN_LCKDET (1 << 30)
+#define PLLC4_BASE_IDDQ      (1 << 18)
+#define PLLC4_OUT3_CLKEN     (1 << 1)
+#define PLLC4_OUT3_RSTN_CLR  (1 << 0)
+
+/*! Generic clock descriptor. */
+typedef struct _clock_t
+{
+	u32 reset;
+	u32 enable;
+	u32 source;
+	u8 index;
+	u8 clk_src;
+	u8 clk_div;
+} clock_t;
+
+/*! Generic clock enable/disable. */
+void clock_enable(const clock_t *clk);
+void clock_disable(const clock_t *clk);
+
+/*! Clock control for specific hardware portions. */
+void clock_enable_fuse(bool enable);
+void clock_enable_uart(u32 idx);
+void clock_disable_uart(u32 idx);
+int  clock_uart_use_src_div(u32 idx, u32 baud);
+void clock_enable_i2c(u32 idx);
+void clock_disable_i2c(u32 idx);
+void clock_enable_se();
+void clock_enable_tzram();
+void clock_enable_host1x();
+void clock_disable_host1x();
+void clock_enable_tsec();
+void clock_disable_tsec();
+void clock_enable_sor_safe();
+void clock_disable_sor_safe();
+void clock_enable_sor0();
+void clock_disable_sor0();
+void clock_enable_sor1();
+void clock_disable_sor1();
+void clock_enable_kfuse();
+void clock_disable_kfuse();
+void clock_enable_cl_dvfs();
+void clock_disable_cl_dvfs();
+void clock_enable_coresight();
+void clock_disable_coresight();
+void clock_enable_pwm();
+void clock_disable_pwm();
+void clock_enable_pllc(u32 divn);
+void clock_disable_pllc();
+void clock_sdmmc_config_clock_source(u32 *pclock, u32 id, u32 val);
+void clock_sdmmc_get_card_clock_div(u32 *pclock, u16 *pdivisor, u32 type);
+int  clock_sdmmc_is_not_reset_and_enabled(u32 id);
+void clock_sdmmc_enable(u32 id, u32 val);
+void clock_sdmmc_disable(u32 id);
+
+#endif

bdk/soc/fuse.c

@@ -0,0 +1,357 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018 shuffle2
+ * Copyright (c) 2018 balika011
+ * Copyright (c) 2019 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <string.h>
+
+#include <soc/fuse.h>
+#include <soc/t210.h>
+
+#define ARRAYSIZE(x) (sizeof(x) / sizeof(*x))
+
+static const u32 evp_thunk_template[] = {
+	0xe92d0007, //   STMFD   SP!, {R0-R2}
+	0xe1a0200e, //   MOV     R2, LR
+	0xe2422002, //   SUB     R2, R2, #2
+	0xe5922000, //   LDR     R2, [R2]
+	0xe20220ff, //   AND     R2, R2, #0xFF
+	0xe1a02082, //   MOV     R2, R2,LSL#1
+	0xe59f001c, //   LDR     R0, =evp_thunk_template
+	0xe59f101c, //   LDR     R1, =thunk_end
+	0xe0411000, //   SUB     R1, R1, R0
+	0xe59f0018, //   LDR     R0, =iram_evp_thunks
+	0xe0800001, //   ADD     R0, R0, R1
+	0xe0822000, //   ADD     R2, R2, R0
+	0xe3822001, //   ORR     R2, R2, #1
+	0xe8bd0003, //   LDMFD   SP!, {R0,R1}
+	0xe12fff12, //   BX      R2
+	0x001007b0, // off_1007EC DCD evp_thunk_template
+	0x001007f8, // off_1007F0 DCD thunk_end
+	0x40004c30, // off_1007F4 DCD iram_evp_thunks
+	// thunk_end is here
+};
+static const u32 evp_thunk_template_len = sizeof(evp_thunk_template);
+
+// treated as 12bit values
+static const u32 hash_vals[] = {1, 2, 4, 8, 0, 3, 5, 6, 7, 9, 10, 11};
+
+void fuse_disable_program()
+{
+	FUSE(FUSE_DISABLEREGPROGRAM) = 1;
+}
+
+u32 fuse_read_odm(u32 idx)
+{
+	return FUSE(FUSE_RESERVED_ODMX(idx));
+}
+
+u32 fuse_read_odm_keygen_rev()
+{
+	if ((fuse_read_odm(4) & 0x800) && fuse_read_odm(0) == 0x8E61ECAE && fuse_read_odm(1) == 0xF2BA3BB2)
+		return (fuse_read_odm(2) & 0x1F);
+
+	return 0;
+}
+
+void fuse_wait_idle()
+{
+	u32 ctrl;
+	do
+	{
+		ctrl = FUSE(FUSE_CTRL);
+	} while (((ctrl >> 16) & 0x1f) != 4);
+}
+
+u32 fuse_read(u32 addr)
+{
+	FUSE(FUSE_ADDR) = addr;
+	FUSE(FUSE_CTRL) = (FUSE(FUSE_ADDR) & ~FUSE_CMD_MASK) | FUSE_READ;
+	fuse_wait_idle();
+	return FUSE(FUSE_RDATA);
+}
+
+void fuse_read_array(u32 *words)
+{
+	for (u32 i = 0; i < 192; i++)
+		words[i] = fuse_read(i);
+}
+
+static u32 _parity32_even(u32 *words, u32 count)
+{
+	u32 acc = words[0];
+	for (u32 i = 1; i < count; i++)
+	{
+		acc ^= words[i];
+	}
+	u32 lo = ((acc & 0xffff) ^ (acc >> 16)) & 0xff;
+	u32 hi = ((acc & 0xffff) ^ (acc >> 16)) >> 8;
+	u32 x = hi ^ lo;
+	lo = ((x & 0xf) ^ (x >> 4)) & 3;
+	hi = ((x & 0xf) ^ (x >> 4)) >> 2;
+	x = hi ^ lo;
+
+	return (x & 1) ^ (x >> 1);
+}
+
+static int _patch_hash_one(u32 *word)
+{
+	u32 bits20_31 = *word & 0xfff00000;
+	u32 parity_bit = _parity32_even(&bits20_31, 1);
+	u32 hash = 0;
+	for (u32 i = 0; i < 12; i++)
+	{
+		if (*word & (1 << (20 + i)))
+		{
+			hash ^= hash_vals[i];
+		}
+	}
+	if (hash == 0)
+	{
+		if (parity_bit == 0)
+		{
+			return 0;
+		}
+		*word ^= 1 << 24;
+		return 1;
+	}
+	if (parity_bit == 0)
+	{
+		return 3;
+	}
+	for (u32 i = 0; i < ARRAYSIZE(hash_vals); i++)
+	{
+		if (hash_vals[i] == hash)
+		{
+			*word ^= 1 << (20 + i);
+			return 1;
+		}
+	}
+	return 2;
+}
+
+static int _patch_hash_multi(u32 *words, u32 count)
+{
+	u32 parity_bit = _parity32_even(words, count);
+	u32 bits0_14 = words[0] & 0x7fff;
+	u32 bit15 = words[0] & 0x8000;
+	u32 bits16_19 = words[0] & 0xf0000;
+
+	u32 hash = 0;
+	words[0] = bits16_19;
+	for (u32 i = 0; i < count; i++)
+	{
+		u32 w = words[i];
+		if (w)
+		{
+			for (u32 bitpos = 0; bitpos < 32; bitpos++)
+			{
+				if ((w >> bitpos) & 1)
+				{
+					hash ^= 0x4000 + i * 32 + bitpos;
+				}
+			}
+		}
+	}
+	hash ^= bits0_14;
+	// stupid but this is what original code does.
+	// equivalent to original words[0] &= 0xfff00000
+	words[0] = bits16_19 ^ bit15 ^ bits0_14;
+
+	if (hash == 0)
+	{
+		if (parity_bit == 0)
+		{
+			return 0;
+		}
+		words[0] ^= 0x8000;
+		return 1;
+	}
+	if (parity_bit == 0)
+	{
+		return 3;
+	}
+	u32 bitcount = hash - 0x4000;
+	if (bitcount < 16 || bitcount >= count * 32)
+	{
+		u32 num_set = 0;
+		for (u32 bitpos = 0; bitpos < 15; bitpos++)
+		{
+			if ((hash >> bitpos) & 1)
+			{
+				num_set++;
+			}
+		}
+		if (num_set != 1)
+		{
+			return 2;
+		}
+		words[0] ^= hash;
+		return 1;
+	}
+	words[bitcount / 32] ^= 1 << (hash & 0x1f);
+	return 1;
+}
+
+int fuse_read_ipatch(void (*ipatch)(u32 offset, u32 value))
+{
+	u32 words[80];
+	u32 word_count;
+	u32 word_addr;
+	u32 word0 = 0;
+	u32 total_read = 0;
+
+	word_count = FUSE(FUSE_FIRST_BOOTROM_PATCH_SIZE);
+	word_count &= 0x7F;
+	word_addr = 191;
+
+	while (word_count)
+	{
+		total_read += word_count;
+		if (total_read >= ARRAYSIZE(words))
+		{
+			break;
+		}
+
+		for (u32 i = 0; i < word_count; i++)
+			words[i] = fuse_read(word_addr--);
+
+		word0 = words[0];
+		if (_patch_hash_multi(words, word_count) >= 2)
+		{
+			return 1;
+		}
+		u32 ipatch_count = (words[0] >> 16) & 0xF;
+		if (ipatch_count)
+		{
+			for (u32 i = 0; i < ipatch_count; i++)
+			{
+				u32 word = words[i + 1];
+				u32 addr = (word >> 16) * 2;
+				u32 data = word & 0xFFFF;
+
+				ipatch(addr, data);
+			}
+		}
+		words[0] = word0;
+		if ((word0 >> 25) == 0)
+			break;
+		if (_patch_hash_one(&word0) >= 2)
+		{
+			return 3;
+		}
+		word_count = word0 >> 25;
+	}
+
+	return 0;
+}
+
+int fuse_read_evp_thunk(u32 *iram_evp_thunks, u32 *iram_evp_thunks_len)
+{
+	u32 words[80];
+	u32 word_count;
+	u32 word_addr;
+	u32 word0 = 0;
+	u32 total_read = 0;
+	int evp_thunk_written = 0;
+	void *evp_thunk_dst_addr = 0;
+
+	memset(iram_evp_thunks, 0, *iram_evp_thunks_len);
+
+	word_count = FUSE(FUSE_FIRST_BOOTROM_PATCH_SIZE);
+	word_count &= 0x7F;
+	word_addr = 191;
+
+	while (word_count)
+	{
+		total_read += word_count;
+		if (total_read >= ARRAYSIZE(words))
+		{
+			break;
+		}
+
+		for (u32 i = 0; i < word_count; i++)
+			words[i] = fuse_read(word_addr--);
+
+		word0 = words[0];
+		if (_patch_hash_multi(words, word_count) >= 2)
+		{
+			return 1;
+		}
+		u32 ipatch_count = (words[0] >> 16) & 0xF;
+		u32 insn_count = word_count - ipatch_count - 1;
+		if (insn_count)
+		{
+			if (!evp_thunk_written)
+			{
+				evp_thunk_dst_addr = (void *)iram_evp_thunks;
+
+				memcpy(evp_thunk_dst_addr, (void *)evp_thunk_template, evp_thunk_template_len);
+				evp_thunk_dst_addr += evp_thunk_template_len;
+				evp_thunk_written = 1;
+				*iram_evp_thunks_len = evp_thunk_template_len;
+
+				//write32(TEGRA_EXCEPTION_VECTORS_BASE + 0x208, iram_evp_thunks);
+			}
+
+			u32 thunk_patch_len = insn_count * sizeof(u32);
+			memcpy(evp_thunk_dst_addr, &words[ipatch_count + 1], thunk_patch_len);
+			evp_thunk_dst_addr += thunk_patch_len;
+			*iram_evp_thunks_len += thunk_patch_len;
+		}
+		words[0] = word0;
+		if ((word0 >> 25) == 0)
+			break;
+		if (_patch_hash_one(&word0) >= 2)
+		{
+			return 3;
+		}
+		word_count = word0 >> 25;
+	}
+
+	return 0;
+}
+
+bool fuse_check_patched_rcm()
+{
+	// Check if XUSB in use.
+	if (FUSE(FUSE_RESERVED_SW) & (1<<7))
+		return true;
+
+	// Check if RCM is ipatched.
+	u32 word_count = FUSE(FUSE_FIRST_BOOTROM_PATCH_SIZE) & 0x7F;
+	u32 word_addr = 191;
+
+	while (word_count)
+	{
+		u32 word0 = fuse_read(word_addr);
+		u32 ipatch_count = (word0 >> 16) & 0xF;
+
+		for (u32 i = 0; i < ipatch_count; i++)
+		{
+			u32 word = fuse_read(word_addr - (i + 1));
+			u32 addr = (word >> 16) * 2;
+			if (addr == 0x769A)
+				return true;
+		}
+
+		word_addr -= word_count;
+		word_count = word0 >> 25;
+	}
+
+	return false;
+}

bdk/soc/fuse.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018 shuffle2
+ * Copyright (c) 2018 balika011
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _FUSE_H_
+#define _FUSE_H_
+
+#include <utils/types.h>
+
+/*! Fuse registers. */
+#define FUSE_CTRL 0x0
+#define FUSE_ADDR 0x4
+#define FUSE_RDATA 0x8
+#define FUSE_WDATA 0xC
+#define FUSE_TIME_RD1 0x10
+#define FUSE_TIME_RD2 0x14
+#define FUSE_TIME_PGM1 0x18
+#define FUSE_TIME_PGM2 0x1C
+#define FUSE_PRIV2INTFC 0x20
+#define FUSE_FUSEBYPASS 0x24
+#define FUSE_PRIVATEKEYDISABLE 0x28
+#define FUSE_DISABLEREGPROGRAM 0x2C
+#define FUSE_WRITE_ACCESS_SW 0x30
+#define FUSE_PWR_GOOD_SW 0x34
+#define FUSE_SKU_INFO 0x110
+#define FUSE_CPU_SPEEDO_0_CALIB 0x114
+#define FUSE_CPU_IDDQ_CALIB 0x118
+#define FUSE_OPT_FT_REV 0x128
+#define FUSE_CPU_SPEEDO_1_CALIB 0x12C
+#define FUSE_CPU_SPEEDO_2_CALIB 0x130
+#define FUSE_SOC_SPEEDO_0_CALIB 0x134
+#define FUSE_SOC_SPEEDO_1_CALIB 0x138
+#define FUSE_SOC_SPEEDO_2_CALIB 0x13C
+#define FUSE_SOC_IDDQ_CALIB 0x140
+#define FUSE_OPT_CP_REV 0x190
+#define FUSE_FIRST_BOOTROM_PATCH_SIZE 0x19c
+#define FUSE_PRIVATE_KEY0 0x1A4
+#define FUSE_PRIVATE_KEY1 0x1A8
+#define FUSE_PRIVATE_KEY2 0x1AC
+#define FUSE_PRIVATE_KEY3 0x1B0
+#define FUSE_PRIVATE_KEY4 0x1B4
+#define FUSE_RESERVED_SW 0x1C0
+#define FUSE_USB_CALIB 0x1F0
+#define FUSE_SKU_DIRECT_CONFIG 0x1F4
+#define FUSE_OPT_VENDOR_CODE 0x200
+#define FUSE_OPT_FAB_CODE 0x204
+#define FUSE_OPT_LOT_CODE_0 0x208
+#define FUSE_OPT_LOT_CODE_1 0x20C
+#define FUSE_OPT_WAFER_ID 0x210
+#define FUSE_OPT_X_COORDINATE 0x214
+#define FUSE_OPT_Y_COORDINATE 0x218
+#define FUSE_GPU_IDDQ_CALIB	0x228
+#define FUSE_USB_CALIB_EXT 0x350
+
+/*! Fuse commands. */
+#define FUSE_READ 0x1
+#define FUSE_WRITE 0x2
+#define FUSE_SENSE 0x3
+#define FUSE_CMD_MASK 0x3
+
+/*! Fuse cache registers. */
+#define FUSE_RESERVED_ODMX(x) (0x1C8 + 4 * (x))
+
+void fuse_disable_program();
+u32 fuse_read_odm(u32 idx);
+u32 fuse_read_odm_keygen_rev();
+void fuse_wait_idle();
+int fuse_read_ipatch(void (*ipatch)(u32 offset, u32 value));
+int fuse_read_evp_thunk(u32 *iram_evp_thunks, u32 *iram_evp_thunks_len);
+void fuse_read_array(u32 *words);
+bool fuse_check_patched_rcm();
+
+#endif

bdk/soc/gpio.c

@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2019 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <soc/gpio.h>
+#include <soc/t210.h>
+
+#define GPIO_BANK_IDX(port)      (port >> 2)
+
+#define GPIO_CNF_OFFSET(port)     (0x00 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_OE_OFFSET(port)      (0x10 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_OUT_OFFSET(port)     (0x20 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_IN_OFFSET(port)      (0x30 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_INT_STA_OFFSET(port) (0x40 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_INT_ENB_OFFSET(port) (0x50 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_INT_LVL_OFFSET(port) (0x60 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_INT_CLR_OFFSET(port) (0x70 + ((port >> 2) << 8) + ((port % 4) << 2))
+
+#define GPIO_CNF_MASKED_OFFSET(port)     (0x80 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_OE_MASKED_OFFSET(port)      (0x90 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_OUT_MASKED_OFFSET(port)     (0xA0 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_INT_STA_MASKED_OFFSET(port) (0xC0 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_INT_ENB_MASKED_OFFSET(port) (0xD0 + ((port >> 2) << 8) + ((port % 4) << 2))
+#define GPIO_INT_LVL_MASKED_OFFSET(port) (0xE0 + ((port >> 2) << 8) + ((port % 4) << 2))
+
+#define GPIO_IRQ_BANK1 32
+#define GPIO_IRQ_BANK2 33
+#define GPIO_IRQ_BANK3 34
+#define GPIO_IRQ_BANK4 35
+#define GPIO_IRQ_BANK5 55
+#define GPIO_IRQ_BANK6 87
+#define GPIO_IRQ_BANK7 89
+#define GPIO_IRQ_BANK8 125
+
+static u8 gpio_bank_irq_ids[8] = {
+	GPIO_IRQ_BANK1, GPIO_IRQ_BANK2, GPIO_IRQ_BANK3, GPIO_IRQ_BANK4,
+	GPIO_IRQ_BANK5, GPIO_IRQ_BANK6, GPIO_IRQ_BANK7, GPIO_IRQ_BANK8
+};
+
+void gpio_config(u32 port, u32 pins, int mode)
+{
+	u32 offset = GPIO_CNF_OFFSET(port);
+
+	if (mode)
+		GPIO(offset) |= pins;
+	else
+		GPIO(offset) &= ~pins;
+
+	(void)GPIO(offset); // Commit the write.
+}
+
+void gpio_output_enable(u32 port, u32 pins, int enable)
+{
+	u32 port_offset = GPIO_OE_OFFSET(port);
+
+	if (enable)
+		GPIO(port_offset) |= pins;
+	else
+		GPIO(port_offset) &= ~pins;
+
+	(void)GPIO(port_offset); // Commit the write.
+}
+
+void gpio_write(u32 port, u32 pins, int high)
+{
+	u32 port_offset = GPIO_OUT_OFFSET(port);
+
+	if (high)
+		GPIO(port_offset) |= pins;
+	else
+		GPIO(port_offset) &= ~pins;
+
+	(void)GPIO(port_offset); // Commit the write.
+}
+
+int gpio_read(u32 port, u32 pins)
+{
+	u32 port_offset = GPIO_IN_OFFSET(port);
+
+	return (GPIO(port_offset) & pins) ? 1 : 0;
+}
+
+static void _gpio_interrupt_clear(u32 port, u32 pins)
+{
+	u32 port_offset = GPIO_INT_CLR_OFFSET(port);
+
+	GPIO(port_offset) |= pins;
+
+	(void)GPIO(port_offset); // Commit the write.
+}
+
+int gpio_interrupt_status(u32 port, u32 pins)
+{
+	u32 port_offset = GPIO_INT_STA_OFFSET(port);
+	u32 enabled = GPIO(GPIO_INT_ENB_OFFSET(port)) & pins;
+
+	int status = ((GPIO(port_offset) & pins) && enabled) ? 1 : 0;
+
+	// Clear the interrupt status.
+	if (status)
+		_gpio_interrupt_clear(port, pins);
+
+	return status;
+}
+
+void gpio_interrupt_enable(u32 port, u32 pins, int enable)
+{
+	u32 port_offset = GPIO_INT_ENB_OFFSET(port);
+
+	// Clear any possible stray interrupt.
+	_gpio_interrupt_clear(port, pins);
+
+	if (enable)
+		GPIO(port_offset) |= pins;
+	else
+		GPIO(port_offset) &= ~pins;
+
+	(void)GPIO(port_offset); // Commit the write.
+}
+
+void gpio_interrupt_level(u32 port, u32 pins, int high, int edge, int delta)
+{
+	u32 port_offset = GPIO_INT_LVL_OFFSET(port);
+
+	u32 val = GPIO(port_offset);
+
+	if (high)
+		val |= pins;
+	else
+		val &= ~pins;
+
+	if (edge)
+		val |= pins << 8;
+	else
+		val &= ~(pins << 8);
+
+	if (delta)
+		val |= pins << 16;
+	else
+		val &= ~(pins << 16);
+
+	GPIO(port_offset) = val;
+
+	(void)GPIO(port_offset); // Commit the write.
+
+	// Clear any possible stray interrupt.
+	_gpio_interrupt_clear(port, pins);
+}
+
+u32 gpio_get_bank_irq_id(u32 port)
+{
+	u32 bank_idx = GPIO_BANK_IDX(port);
+
+	return gpio_bank_irq_ids[bank_idx];
+}

bdk/soc/gpio.h

@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2019 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+#include <utils/types.h>
+
+#define GPIO_MODE_SPIO 0
+#define GPIO_MODE_GPIO 1
+
+#define GPIO_OUTPUT_DISABLE 0
+#define GPIO_OUTPUT_ENABLE 1
+
+#define GPIO_IRQ_DISABLE 0
+#define GPIO_IRQ_ENABLE 1
+
+#define GPIO_LOW 0
+#define GPIO_HIGH 1
+#define GPIO_FALLING 0
+#define GPIO_RISING 1
+
+#define GPIO_LEVEL 0
+#define GPIO_EDGE 1
+
+#define GPIO_CONFIGURED_EDGE 0
+#define GPIO_ANY_EDGE_CHANGE 1
+
+/*! GPIO pins (0-7 for each port). */
+#define GPIO_PIN_0 (1 << 0)
+#define GPIO_PIN_1 (1 << 1)
+#define GPIO_PIN_2 (1 << 2)
+#define GPIO_PIN_3 (1 << 3)
+#define GPIO_PIN_4 (1 << 4)
+#define GPIO_PIN_5 (1 << 5)
+#define GPIO_PIN_6 (1 << 6)
+#define GPIO_PIN_7 (1 << 7)
+
+/*! GPIO ports (A-EE). */
+#define GPIO_PORT_A 0
+#define GPIO_PORT_B 1
+#define GPIO_PORT_C 2
+#define GPIO_PORT_D 3
+#define GPIO_PORT_E 4
+#define GPIO_PORT_F 5
+#define GPIO_PORT_G 6
+#define GPIO_PORT_H 7
+#define GPIO_PORT_I 8
+#define GPIO_PORT_J 9
+#define GPIO_PORT_K 10
+#define GPIO_PORT_L 11
+#define GPIO_PORT_M 12
+#define GPIO_PORT_N 13
+#define GPIO_PORT_O 14
+#define GPIO_PORT_P 15
+#define GPIO_PORT_Q 16
+#define GPIO_PORT_R 17
+#define GPIO_PORT_S 18
+#define GPIO_PORT_T 19
+#define GPIO_PORT_U 20
+#define GPIO_PORT_V 21
+#define GPIO_PORT_W 22
+#define GPIO_PORT_X 23
+#define GPIO_PORT_Y 24
+#define GPIO_PORT_Z 25
+#define GPIO_PORT_AA 26
+#define GPIO_PORT_BB 27
+#define GPIO_PORT_CC 28
+#define GPIO_PORT_DD 29
+#define GPIO_PORT_EE 30
+
+void gpio_config(u32 port, u32 pins, int mode);
+void gpio_output_enable(u32 port, u32 pins, int enable);
+void gpio_write(u32 port, u32 pins, int high);
+int  gpio_read(u32 port, u32 pins);
+int  gpio_interrupt_status(u32 port, u32 pins);
+void gpio_interrupt_enable(u32 port, u32 pins, int enable);
+void gpio_interrupt_level(u32 port, u32 pins, int high, int edge, int delta);
+u32  gpio_get_bank_irq_id(u32 port);
+
+#endif

bdk/soc/hw_init.c

@@ -0,0 +1,386 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018-2020 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <string.h>
+
+#include <soc/hw_init.h>
+#include <gfx/di.h>
+#include <input/joycon.h>
+#include <input/touch.h>
+#include <sec/se.h>
+#include <sec/se_t210.h>
+#include <soc/bpmp.h>
+#include <soc/clock.h>
+#include <soc/fuse.h>
+#include <soc/gpio.h>
+#include <soc/i2c.h>
+#include <soc/pinmux.h>
+#include <soc/pmc.h>
+#include <soc/uart.h>
+#include <soc/t210.h>
+#include <mem/mc.h>
+#include <mem/minerva.h>
+#include <mem/sdram.h>
+#include <power/bq24193.h>
+#include <power/max77620.h>
+#include <power/max7762x.h>
+#include <power/regulator_5v.h>
+#include <storage/nx_sd.h>
+#include <storage/sdmmc.h>
+#include <thermal/fan.h>
+#include <utils/util.h>
+
+extern boot_cfg_t b_cfg;
+extern volatile nyx_storage_t *nyx_str;
+
+/*
+ * CLK_OSC - 38.4 MHz crystal.
+ * CLK_M   - 19.2 MHz (osc/2).
+ * CLK_S   - 32.768 KHz (from PMIC).
+ * SCLK    - 204MHz init (-> 408MHz -> OC).
+ * HCLK    - 204MHz init (-> 408MHz -> OC).
+ * PCLK    - 68MHz  init (-> 136MHz -> OC/4).
+ */
+
+void _config_oscillators()
+{
+	CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 4; // Set CLK_M_DIVISOR to 2.
+	SYSCTR0(SYSCTR0_CNTFID0) = 19200000;             // Set counter frequency.
+	TMR(TIMERUS_USEC_CFG) = 0x45F;                   // For 19.2MHz clk_m.
+	CLOCK(CLK_RST_CONTROLLER_OSC_CTRL) = 0x50000071; // Set OSC to 38.4MHz and drive strength.
+
+	PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFFFFF81) | 0xE; // Set LP0 OSC drive strength.
+	PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFBFFFFF) | PMC_OSC_EDPD_OVER_OSC_CTRL_OVER;
+	PMC(APBDEV_PMC_CNTRL2) = (PMC(APBDEV_PMC_CNTRL2) & 0xFFFFEFFF) | PMC_CNTRL2_HOLD_CKE_LOW_EN;
+	PMC(APBDEV_PMC_SCRATCH188) = (PMC(APBDEV_PMC_SCRATCH188) & 0xFCFFFFFF) | (4 << 23); // LP0 EMC2TMC_CFG_XM2COMP_PU_VREF_SEL_RANGE.
+
+	CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 0x10;   // Set HCLK div to 2 and PCLK div to 1.
+	CLOCK(CLK_RST_CONTROLLER_PLLMB_BASE) &= 0xBFFFFFFF; // PLLMB disable.
+
+	PMC(APBDEV_PMC_TSC_MULT) = (PMC(APBDEV_PMC_TSC_MULT) & 0xFFFF0000) | 0x249F; //0x249F = 19200000 * (16 / 32.768 kHz)
+
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SYS) = 0;              // Set SCLK div to 1.
+	CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444;  // Set clk source to Run and PLLP_OUT2 (204MHz).
+	CLOCK(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER) = 0x80000000; // Enable SUPER_SDIV to 1.
+	CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2;             // Set HCLK div to 1 and PCLK div to 3.
+}
+
+void _config_gpios()
+{
+	PINMUX_AUX(PINMUX_AUX_UART2_TX) = 0;
+	PINMUX_AUX(PINMUX_AUX_UART3_TX) = 0;
+
+	// Set Joy-Con IsAttached direction.
+	PINMUX_AUX(PINMUX_AUX_GPIO_PE6) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE;
+	PINMUX_AUX(PINMUX_AUX_GPIO_PH6) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE;
+
+	// Set pin mode for Joy-Con IsAttached and UARTB/C TX pins.
+#if !defined (DEBUG_UART_PORT) || DEBUG_UART_PORT != UART_B
+	gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_GPIO);
+#endif
+#if !defined (DEBUG_UART_PORT) || DEBUG_UART_PORT != UART_C
+	gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_GPIO);
+#endif
+	// Set Joy-Con IsAttached mode.
+	gpio_config(GPIO_PORT_E, GPIO_PIN_6, GPIO_MODE_GPIO);
+	gpio_config(GPIO_PORT_H, GPIO_PIN_6, GPIO_MODE_GPIO);
+
+	// Enable input logic for Joy-Con IsAttached and UARTB/C TX pins.
+	gpio_output_enable(GPIO_PORT_G, GPIO_PIN_0, GPIO_OUTPUT_DISABLE);
+	gpio_output_enable(GPIO_PORT_D, GPIO_PIN_1, GPIO_OUTPUT_DISABLE);
+	gpio_output_enable(GPIO_PORT_E, GPIO_PIN_6, GPIO_OUTPUT_DISABLE);
+	gpio_output_enable(GPIO_PORT_H, GPIO_PIN_6, GPIO_OUTPUT_DISABLE);
+
+	pinmux_config_i2c(I2C_1);
+	pinmux_config_i2c(I2C_5);
+	pinmux_config_uart(UART_A);
+
+	// Configure volume up/down as inputs.
+	gpio_config(GPIO_PORT_X, GPIO_PIN_6, GPIO_MODE_GPIO);
+	gpio_config(GPIO_PORT_X, GPIO_PIN_7, GPIO_MODE_GPIO);
+	gpio_output_enable(GPIO_PORT_X, GPIO_PIN_6, GPIO_OUTPUT_DISABLE);
+	gpio_output_enable(GPIO_PORT_X, GPIO_PIN_7, GPIO_OUTPUT_DISABLE);
+
+	// Configure HOME as inputs.
+	// PINMUX_AUX(PINMUX_AUX_BUTTON_HOME) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE;
+	// gpio_config(GPIO_PORT_Y, GPIO_PIN_1, GPIO_MODE_GPIO);
+}
+
+void _config_pmc_scratch()
+{
+	PMC(APBDEV_PMC_SCRATCH20) &= 0xFFF3FFFF;  // Unset Debug console from Customer Option.
+	PMC(APBDEV_PMC_SCRATCH190) &= 0xFFFFFFFE; // Unset DATA_DQ_E_IVREF EMC_PMACRO_DATA_PAD_TX_CTRL
+	PMC(APBDEV_PMC_SECURE_SCRATCH21) |= PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT;
+}
+
+void _mbist_workaround()
+{
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= (1 << 10); // Enable AHUB clock.
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= (1 <<  6); // Enable APE clock.
+
+	// Set mux output to SOR1 clock switch.
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) | 0x8000) & 0xFFFFBFFF;
+	// Enabled PLLD and set csi to PLLD for test pattern generation.
+	CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) |= 0x40800000;
+
+	// Clear per-clock resets.
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_CLR) = 0x40;       // Clear reset APE.
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_CLR) = 0x40000;    // Clear reset VIC.
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = 0x18000000; // Clear reset DISP1, HOST1X.
+	usleep(2);
+
+	// I2S channels to master and disable SLCG.
+	I2S(I2S1_CTRL) |= I2S_CTRL_MASTER_EN;
+	I2S(I2S1_CG)   &= ~I2S_CG_SLCG_ENABLE;
+	I2S(I2S2_CTRL) |= I2S_CTRL_MASTER_EN;
+	I2S(I2S2_CG)   &= ~I2S_CG_SLCG_ENABLE;
+	I2S(I2S3_CTRL) |= I2S_CTRL_MASTER_EN;
+	I2S(I2S3_CG)   &= ~I2S_CG_SLCG_ENABLE;
+	I2S(I2S4_CTRL) |= I2S_CTRL_MASTER_EN;
+	I2S(I2S4_CG)   &= ~I2S_CG_SLCG_ENABLE;
+	I2S(I2S5_CTRL) |= I2S_CTRL_MASTER_EN;
+	I2S(I2S5_CG)   &= ~I2S_CG_SLCG_ENABLE;
+
+	DISPLAY_A(_DIREG(DC_COM_DSC_TOP_CTL)) |= 4; // DSC_SLCG_OVERRIDE.
+	VIC(0x8C) = 0xFFFFFFFF;
+	usleep(2);
+
+	// Set per-clock reset.
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_Y_SET) = 0x40;       // Set reset APE.
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = 0x18000000; // Set reset DISP1, HOST1x.
+	CLOCK(CLK_RST_CONTROLLER_RST_DEV_X_SET) = 0x40000;    // Set reset VIC.
+
+	// Enable specific clocks and disable all others.
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_H) = 0xC0;       // Enable clock PMC, FUSE.
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) = 0x80000130; // Enable clock RTC, TMR, GPIO, BPMP_CACHE.
+	//CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) = 0x80400130; // Keep USBD ON.
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_U) = 0x1F00200;  // Enable clock CSITE, IRAMA, IRAMB, IRAMC, IRAMD, BPMP_CACHE_RAM.
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) = 0x80400808; // Enable clock MSELECT, APB2APE, SPDIF_DOUBLER, SE.
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_W) = 0x402000FC; // Enable clock PCIERX0, PCIERX1, PCIERX2, PCIERX3, PCIERX4, PCIERX5, ENTROPY, MC1.
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_X) = 0x23000780; // Enable clock MC_CAPA, MC_CAPB, MC_CPU, MC_BBC, DBGAPB, HPLL_ADSP, PLLG_REF.
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) = 0x300;      // Enable clock MC_CDPA, MC_CCPA.
+
+	// Disable clock gate overrides.
+	CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA) = 0;
+	CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB) = 0;
+	CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC) = 0;
+	CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) = 0;
+	CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE) = 0;
+
+	// Set child clock sources.
+	CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) &= 0x1F7FFFFF; // Disable PLLD and set reference clock and csi clock.
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) &= 0xFFFF3FFF; // Set SOR1 to automatic muxing of safe clock (24MHz) or SOR1 clk switch.
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT.
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT.
+	CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT.
+}
+
+void _config_se_brom()
+{
+	// Enable fuse clock.
+	clock_enable_fuse(true);
+
+	// Skip SBK/SSK if sept was run.
+	if (!(b_cfg.boot_cfg & BOOT_CFG_SEPT_RUN))
+	{
+		// Bootrom part we skipped.
+		u32 sbk[4] = {
+			FUSE(FUSE_PRIVATE_KEY0),
+			FUSE(FUSE_PRIVATE_KEY1),
+			FUSE(FUSE_PRIVATE_KEY2),
+			FUSE(FUSE_PRIVATE_KEY3)
+		};
+		// Set SBK to slot 14.
+		se_aes_key_set(14, sbk, 0x10);
+
+		// Lock SBK from being read.
+		se_key_acc_ctrl(14, SE_KEY_TBL_DIS_KEYREAD_FLAG);
+
+		// Lock SSK (although it's not set and unused anyways).
+		se_key_acc_ctrl(15, SE_KEY_TBL_DIS_KEYREAD_FLAG);
+	}
+
+	// This memset needs to happen here, else TZRAM will behave weirdly later on.
+	memset((void *)TZRAM_BASE, 0, 0x10000);
+	PMC(APBDEV_PMC_CRYPTO_OP) = PMC_CRYPTO_OP_SE_ENABLE;
+	SE(SE_INT_STATUS_REG_OFFSET) = 0x1F;
+
+	// Clear the boot reason to avoid problems later
+	PMC(APBDEV_PMC_SCRATCH200) = 0x0;
+	PMC(APBDEV_PMC_RST_STATUS) = 0x0;
+	APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) = (APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) & 0xF0) | (7 << 10);
+}
+
+void _config_regulators()
+{
+	// Disable low battery shutdown monitor.
+	max77620_low_battery_monitor_config(false);
+
+	// Disable SDMMC1 IO power.
+	gpio_output_enable(GPIO_PORT_E, GPIO_PIN_4, GPIO_OUTPUT_DISABLE);
+	max77620_regulator_enable(REGULATOR_LDO2, 0);
+	sd_power_cycle_time_start = get_tmr_ms();
+
+	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CNFGBBC, MAX77620_CNFGBBC_RESISTOR_1K);
+	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1,
+		(1 << 6) | (3 << MAX77620_ONOFFCNFG1_MRT_SHIFT)); // PWR delay for forced shutdown off.
+
+	// Configure all Flexible Power Sequencers.
+	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG0,
+		(7 << MAX77620_FPS_TIME_PERIOD_SHIFT));
+	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG1,
+		(7 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (1 << MAX77620_FPS_EN_SRC_SHIFT));
+	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG2,
+		(7 << MAX77620_FPS_TIME_PERIOD_SHIFT));
+	max77620_regulator_config_fps(REGULATOR_LDO4);
+	max77620_regulator_config_fps(REGULATOR_LDO8);
+	max77620_regulator_config_fps(REGULATOR_SD0);
+	max77620_regulator_config_fps(REGULATOR_SD1);
+	max77620_regulator_config_fps(REGULATOR_SD3);
+
+	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_GPIO3,
+		(4 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (2 << MAX77620_FPS_PD_PERIOD_SHIFT)); // 3.x+
+
+	// Set vdd_core voltage to 1.125V.
+	max77620_regulator_set_voltage(REGULATOR_SD0, 1125000);
+
+	// Fix CPU/GPU after a L4T warmboot.
+	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, 2);
+	i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO6, 2);
+
+	i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_0_95V); // Disable power.
+	i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_DVS_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_1_09V); // Enable DVS power.
+	i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL1_REG, MAX77621_RAMP_50mV_PER_US);
+	i2c_send_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL2_REG,
+		MAX77621_T_JUNCTION_120 | MAX77621_FT_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS |
+		MAX77621_CKKADV_TRIP_150mV_PER_US | MAX77621_INDUCTOR_NOMINAL);
+
+	i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_0_95V); // Disable power.
+	i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_VOUT_DVS_REG, MAX77621_VOUT_ENABLE | MAX77621_VOUT_1_09V); // Enable DVS power.
+	i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_CONTROL1_REG, MAX77621_RAMP_50mV_PER_US);
+	i2c_send_byte(I2C_5, MAX77621_GPU_I2C_ADDR, MAX77621_CONTROL2_REG,
+		MAX77621_T_JUNCTION_120 | MAX77621_FT_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS |
+		MAX77621_CKKADV_TRIP_150mV_PER_US | MAX77621_INDUCTOR_NOMINAL);
+}
+
+void config_hw()
+{
+	// Bootrom stuff we skipped by going through rcm.
+	_config_se_brom();
+	//FUSE(FUSE_PRIVATEKEYDISABLE) = 0x11;
+	SYSREG(AHB_AHB_SPARE_REG) &= 0xFFFFFF9F; // Unset APB2JTAG_OVERRIDE_EN and OBS_OVERRIDE_EN.
+	PMC(APBDEV_PMC_SCRATCH49) = PMC(APBDEV_PMC_SCRATCH49) & 0xFFFFFFFC;
+
+	_mbist_workaround();
+	clock_enable_se();
+
+	// Enable fuse clock.
+	clock_enable_fuse(true);
+
+	// Disable fuse programming.
+	fuse_disable_program();
+
+	mc_enable();
+
+	_config_oscillators();
+	APB_MISC(APB_MISC_PP_PINMUX_GLOBAL) = 0;
+	_config_gpios();
+
+#ifdef DEBUG_UART_PORT
+	clock_enable_uart(DEBUG_UART_PORT);
+	uart_init(DEBUG_UART_PORT, 115200);
+#endif
+
+	clock_enable_cl_dvfs();
+
+	clock_enable_i2c(I2C_1);
+	clock_enable_i2c(I2C_5);
+
+	clock_enable_tzram();
+
+	i2c_init(I2C_1);
+	i2c_init(I2C_5);
+
+	// Enable charger in case it's disabled.
+	bq24193_enable_charger();
+
+	_config_regulators();
+
+	_config_pmc_scratch(); // Missing from 4.x+
+
+	CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // Set SCLK to PLLP_OUT (408MHz).
+
+	sdram_init();
+
+	bpmp_mmu_enable();
+	mc_enable_ahb_redirect();
+
+	// Clear flags from PMC_SCRATCH0
+	PMC(APBDEV_PMC_SCRATCH0) &= ~PMC_SCRATCH0_MODE_PAYLOAD;
+}
+
+void reconfig_hw_workaround(bool extra_reconfig, u32 magic)
+{
+	// Disable BPMP max clock.
+	bpmp_clk_rate_set(BPMP_CLK_NORMAL);
+
+#ifdef NYX
+	// Deinit touchscreen, 5V regulators and Joy-Con.
+	touch_power_off();
+	set_fan_duty(0);
+	jc_deinit();
+	regulator_disable_5v(REGULATOR_5V_ALL);
+	clock_disable_uart(UART_B);
+	clock_disable_uart(UART_C);
+#endif
+
+	// Flush/disable MMU cache and set DRAM clock to 204MHz.
+	bpmp_mmu_disable();
+	minerva_change_freq(FREQ_204);
+	nyx_str->mtc_cfg.init_done = 0;
+
+	// Re-enable clocks to Audio Processing Engine as a workaround to hanging.
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= (1 << 10); // Enable AHUB clock.
+	CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= (1 <<  6); // Enable APE clock.
+
+	if (extra_reconfig)
+	{
+		msleep(10);
+		PMC(APBDEV_PMC_PWR_DET_VAL) |= PMC_PWR_DET_SDMMC1_IO_EN;
+
+		clock_disable_cl_dvfs();
+
+		// Disable Joy-con GPIOs.
+		gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO);
+		gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO);
+		gpio_config(GPIO_PORT_E, GPIO_PIN_6, GPIO_MODE_SPIO);
+		gpio_config(GPIO_PORT_H, GPIO_PIN_6, GPIO_MODE_SPIO);
+	}
+
+	// Power off display.
+	display_end();
+
+	// Enable clock to USBD and init SDMMC1 to avoid hangs with bad hw inits.
+	if (magic == 0xBAADF00D)
+	{
+		CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) |= (1 << 22);
+		sdmmc_init(&sd_sdmmc, SDMMC_1, SDMMC_POWER_3_3, SDMMC_BUS_WIDTH_1, SDHCI_TIMING_SD_ID, 0);
+		clock_disable_cl_dvfs();
+
+		msleep(200);
+	}
+}

bdk/soc/hw_init.h

@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _HW_INIT_H_
+#define _HW_INIT_H_
+
+#include <utils/types.h>
+
+void config_hw();
+void reconfig_hw_workaround(bool extra_reconfig, u32 magic);
+
+#endif

bdk/soc/i2c.c

@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018-2020 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <string.h>
+
+#include <soc/i2c.h>
+#include <utils/util.h>
+
+static const u32 i2c_addrs[] = {
+	0x7000C000, 0x7000C400, 0x7000C500,
+	0x7000C700, 0x7000D000, 0x7000D100
+};
+
+static void _i2c_wait(vu32 *base)
+{
+	base[I2C_CONFIG_LOAD] = 0x25;
+	for (u32 i = 0; i < 20; i++)
+	{
+		usleep(1);
+		if (!(base[I2C_CONFIG_LOAD] & 1))
+			break;
+	}
+}
+
+static int _i2c_send_pkt(u32 idx, u32 x, u8 *buf, u32 size)
+{
+	if (size > 8)
+		return 0;
+
+	u32 tmp = 0;
+
+	vu32 *base = (vu32 *)i2c_addrs[idx];
+	base[I2C_CMD_ADDR0] = x << 1; //Set x (send mode).
+
+	if (size > 4)
+	{
+		memcpy(&tmp, buf, 4);
+		base[I2C_CMD_DATA1] = tmp; //Set value.
+		tmp = 0;
+		memcpy(&tmp, buf + 4, size - 4);
+		base[I2C_CMD_DATA2] = tmp;
+	}
+	else
+	{
+		memcpy(&tmp, buf, size);
+		base[I2C_CMD_DATA1] = tmp; //Set value.
+	}
+
+	base[I2C_CNFG] = ((size - 1) << 1) | 0x2800; //Set size and send mode.
+	_i2c_wait(base);                             //Kick transaction.
+
+	base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFFDFF) | 0x200;
+
+	u32 timeout = get_tmr_ms() + 1500;
+	while (base[I2C_STATUS] & 0x100)
+	{
+		if (get_tmr_ms() > timeout)
+			return 0;
+	}
+
+	if (base[I2C_STATUS] << 28)
+		return 0;
+
+	return 1;
+}
+
+static int _i2c_recv_pkt(u32 idx, u8 *buf, u32 size, u32 x)
+{
+	if (size > 8)
+		return 0;
+
+	vu32 *base = (vu32 *)i2c_addrs[idx];
+	base[I2C_CMD_ADDR0] = (x << 1) | 1;          // Set x (recv mode).
+	base[I2C_CNFG] = ((size - 1) << 1) | 0x2840; // Set size and recv mode.
+	_i2c_wait(base);                             // Kick transaction.
+
+	base[I2C_CNFG] = (base[I2C_CNFG] & 0xFFFFFDFF) | 0x200;
+
+	u32 timeout = get_tmr_ms() + 1500;
+	while (base[I2C_STATUS] & 0x100)
+	{
+		if (get_tmr_ms() > timeout)
+			return 0;
+	}
+
+	if (base[I2C_STATUS] << 28)
+		return 0;
+
+	u32 tmp = base[I2C_CMD_DATA1]; // Get LS value.
+	if (size > 4)
+	{
+		memcpy(buf, &tmp, 4);
+		tmp = base[I2C_CMD_DATA2]; // Get MS value.
+		memcpy(buf + 4, &tmp, size - 4);
+	}
+	else
+		memcpy(buf, &tmp, size);
+
+	return 1;
+}
+
+void i2c_init(u32 idx)
+{
+	vu32 *base = (vu32 *)i2c_addrs[idx];
+
+	base[I2C_CLK_DIVISOR_REGISTER] = 0x50001;
+	base[I2C_BUS_CLEAR_CONFIG] = 0x90003;
+	_i2c_wait(base);
+
+	for (u32 i = 0; i < 10; i++)
+	{
+		usleep(20000);
+		if (base[INTERRUPT_STATUS_REGISTER] & 0x800)
+			break;
+	}
+
+	(vu32)base[I2C_BUS_CLEAR_STATUS];
+	base[INTERRUPT_STATUS_REGISTER] = base[INTERRUPT_STATUS_REGISTER];
+}
+
+int i2c_send_buf_small(u32 idx, u32 x, u32 y, u8 *buf, u32 size)
+{
+	u8 tmp[4];
+
+	if (size > 7)
+		return 0;
+
+	tmp[0] = y;
+	memcpy(tmp + 1, buf, size);
+
+	return _i2c_send_pkt(idx, x, tmp, size + 1);
+}
+
+int i2c_recv_buf(u8 *buf, u32 size, u32 idx, u32 x)
+{
+	return _i2c_recv_pkt(idx, buf, size, x);
+}
+
+int i2c_recv_buf_small(u8 *buf, u32 size, u32 idx, u32 x, u32 y)
+{
+	int res = _i2c_send_pkt(idx, x, (u8 *)&y, 1);
+	if (res)
+		res = _i2c_recv_pkt(idx, buf, size, x);
+	return res;
+}
+
+int i2c_send_byte(u32 idx, u32 x, u32 y, u8 b)
+{
+	return i2c_send_buf_small(idx, x, y, &b, 1);
+}
+
+u8 i2c_recv_byte(u32 idx, u32 x, u32 y)
+{
+	u8 tmp = 0;
+	i2c_recv_buf_small(&tmp, 1, idx, x, y);
+	return tmp;
+}
+

bdk/soc/i2c.h

@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2020 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _I2C_H_
+#define _I2C_H_
+
+#include <utils/types.h>
+
+#define I2C_1 0
+#define I2C_2 1
+#define I2C_3 2
+#define I2C_4 3
+#define I2C_5 4
+#define I2C_6 5
+
+#define I2C_CNFG        0x00
+#define I2C_CMD_ADDR0   0x01
+#define I2C_CMD_DATA1   0x03
+#define I2C_CMD_DATA2   0x04
+#define I2C_STATUS 0x07
+#define INTERRUPT_STATUS_REGISTER 0x1A
+#define I2C_CLK_DIVISOR_REGISTER 0x1B
+#define I2C_BUS_CLEAR_CONFIG 0x21
+#define I2C_BUS_CLEAR_STATUS 0x22
+#define I2C_CONFIG_LOAD 0x23
+
+void i2c_init(u32 idx);
+int i2c_send_buf_small(u32 idx, u32 x, u32 y, u8 *buf, u32 size);
+int i2c_recv_buf(u8 *buf, u32 size, u32 idx, u32 x);
+int i2c_recv_buf_small(u8 *buf, u32 size, u32 idx, u32 x, u32 y);
+int i2c_send_byte(u32 idx, u32 x, u32 y, u8 b);
+u8 i2c_recv_byte(u32 idx, u32 x, u32 y);
+
+#endif

bdk/soc/irq.c

@@ -0,0 +1,263 @@
+/*
+ * BPMP-Lite IRQ driver for Tegra X1
+ *
+ * Copyright (c) 2019 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <string.h>
+
+#include "irq.h"
+#include <soc/t210.h>
+#include <gfx_utils.h>
+#include <mem/heap.h>
+
+//#define DPRINTF(...) gfx_printf(__VA_ARGS__)
+#define DPRINTF(...)
+
+extern void irq_disable();
+extern void irq_enable_cpu_irq_exceptions();
+extern void irq_disable_cpu_irq_exceptions();
+
+typedef struct _irq_ctxt_t
+{
+	u32  irq;
+	int  (*handler)(u32 irq, void *data);
+	void *data;
+	u32  flags;
+} irq_ctxt_t;
+
+bool irq_init_done = false;
+irq_ctxt_t irqs[IRQ_MAX_HANDLERS];
+
+static void _irq_enable_source(u32 irq)
+{
+	u32 ctrl_idx = irq >> 5;
+	u32 bit = irq % 32;
+
+	// Set as normal IRQ.
+	ICTLR(ctrl_idx, PRI_ICTLR_COP_IEP_CLASS) &= ~(1 << bit);
+
+	// Enable IRQ source.
+	ICTLR(ctrl_idx, PRI_ICTLR_COP_IER_SET) = 1 << bit;
+}
+
+static void _irq_disable_source(u32 irq)
+{
+	u32 ctrl_idx = irq >> 5;
+	u32 bit = irq % 32;
+
+	// Disable IRQ source.
+	ICTLR(ctrl_idx, PRI_ICTLR_COP_IER_CLR) = 1 << bit;
+}
+
+static void _irq_disable_and_ack_all()
+{
+	// Disable and ack all IRQ sources.
+	for (u32 ctrl_idx = 0; ctrl_idx < 6; ctrl_idx++)
+	{
+		u32 enabled_irqs = ICTLR(ctrl_idx, PRI_ICTLR_COP_IER);
+		ICTLR(ctrl_idx, PRI_ICTLR_COP_IER_CLR) = enabled_irqs;
+		ICTLR(ctrl_idx, PRI_ICTLR_FIR_CLR) = enabled_irqs;
+	}
+}
+
+static void _irq_ack_source(u32 irq)
+{
+	u32 ctrl_idx = irq >> 5;
+	u32 bit = irq % 32;
+
+	// Force stop the interrupt as it's serviced here.
+	ICTLR(ctrl_idx, PRI_ICTLR_FIR_CLR) = 1 << bit;
+}
+
+void irq_free(u32 irq)
+{
+	for (u32 idx = 0; idx < IRQ_MAX_HANDLERS; idx++)
+	{
+		if (irqs[idx].irq == irq && irqs[idx].handler)
+		{
+			irqs[idx].irq = 0;
+			irqs[idx].handler = NULL;
+			irqs[idx].data = NULL;
+			irqs[idx].flags = 0;
+
+			_irq_disable_source(irq);
+		}
+	}
+}
+
+static void _irq_free_all()
+{
+	for (u32 idx = 0; idx < IRQ_MAX_HANDLERS; idx++)
+	{
+		if (irqs[idx].handler)
+		{
+			_irq_disable_source(irqs[idx].irq);
+
+			irqs[idx].irq = 0;
+			irqs[idx].handler = NULL;
+			irqs[idx].data = NULL;
+			irqs[idx].flags = 0;
+		}
+	}
+}
+
+static irq_status_t _irq_handle_source(u32 irq)
+{
+	int status = IRQ_NONE;
+
+	_irq_disable_source(irq);
+	_irq_ack_source(irq);
+
+	u32 idx;
+	for (idx = 0; idx < IRQ_MAX_HANDLERS; idx++)
+	{
+		if (irqs[idx].irq == irq)
+		{
+			status = irqs[idx].handler(irqs[idx].irq, irqs[idx].data);
+
+			if (status == IRQ_HANDLED)
+				break;
+		}
+	}
+
+	if (irqs[idx].flags & IRQ_FLAG_ONE_OFF)
+		irq_free(irq);
+	else
+		_irq_enable_source(irq);
+
+	return status;
+}
+
+void irq_handler()
+{
+	// Get IRQ source.
+	u32 irq = EXCP_VEC(EVP_COP_IRQ_STS) & 0xFF;
+
+	if (!irq_init_done)
+	{
+		_irq_ack_source(irq);
+		return;
+	}
+
+	DPRINTF("IRQ: %d\n", irq);
+
+	int err = _irq_handle_source(irq);
+
+	//TODO: disable if unhandhled.
+	if (err == IRQ_NONE)
+		gfx_printf("Unhandled IRQ: %d\n", irq);
+}
+
+static void _irq_init()
+{
+	_irq_disable_and_ack_all();
+	memset(irqs, 0, sizeof(irq_ctxt_t) * IRQ_MAX_HANDLERS);
+	irq_init_done = true;
+}
+
+void irq_end()
+{
+	_irq_free_all();
+	irq_disable_cpu_irq_exceptions();
+	irq_init_done = false;
+}
+
+void irq_wait_event(u32 irq)
+{
+	irq_disable_cpu_irq_exceptions();
+
+	_irq_enable_source(irq);
+
+	// Halt BPMP and wait for the IRQ. No need to use WAIT_EVENT + LIC_IRQ when BPMP serves the IRQ.
+	FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_STOP_UNTIL_IRQ;
+
+	_irq_disable_source(irq);
+	_irq_ack_source(irq);
+
+	irq_enable_cpu_irq_exceptions();
+}
+
+void irq_disable_wait_event()
+{
+	irq_enable_cpu_irq_exceptions();
+}
+
+irq_status_t irq_request(u32 irq, irq_handler_t handler, void *data, irq_flags_t flags)
+{
+	if (!irq_init_done)
+		_irq_init();
+
+	for (u32 idx = 0; idx < IRQ_MAX_HANDLERS; idx++)
+	{
+		if (irqs[idx].handler == NULL ||
+			(irqs[idx].irq == irq && irqs[idx].flags & IRQ_FLAG_REPLACEABLE))
+		{
+			DPRINTF("Registered handler, IRQ: %d, Slot: %d\n", irq, idx);
+			DPRINTF("Handler: %08p, Flags: %x\n", (u32)handler, flags);
+
+			irqs[idx].irq = irq;
+			irqs[idx].handler = handler;
+			irqs[idx].data = data;
+			irqs[idx].flags = flags;
+
+			_irq_enable_source(irq);
+
+			return IRQ_ENABLED;
+		}
+		else if (irqs[idx].irq == irq)
+			return IRQ_ALREADY_REGISTERED;
+	}
+
+	return IRQ_NO_SLOTS_AVAILABLE;
+}
+
+void __attribute__ ((target("arm"))) fiq_setup()
+{
+/*
+	asm volatile("mrs r12, cpsr\n\t"
+		"bic r12, r12, #0x1F\n\t"
+		"orr r12, r12, #0x11\n\t"
+		"msr cpsr_c, r12\n\t");
+
+	register volatile char *text asm ("r8");
+	register volatile char *uart_tx asm ("r9");
+	register int len asm ("r10");
+
+	len = 5;
+	uart_tx = (char *)0x70006040;
+	memcpy((char *)text, "FIQ\r\n", len);
+	*uart_tx = 0;
+
+	asm volatile("mrs r12, cpsr\n"
+		"orr r12, r12, #0x1F\n"
+		"msr cpsr_c, r12");
+*/
+}
+
+void  __attribute__ ((target("arm"), interrupt ("FIQ"))) fiq_handler()
+{
+/*
+	register volatile char *text asm ("r8");
+	register volatile char *uart_tx asm ("r9");
+	register int len asm ("r10");
+
+	while (len)
+	{
+		*uart_tx = *text++;
+		len--;
+	}
+*/
+}

bdk/soc/irq.h

@@ -0,0 +1,222 @@
+/*
+ * BPMP-Lite IRQ driver for Tegra X1
+ *
+ * Copyright (c) 2019 CTCaer
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef IRQ_H
+#define IRQ_H
+
+#include <utils/types.h>
+
+#define IRQ_MAX_HANDLERS 16
+
+/* Primary interrupt controller ids */
+#define IRQ_TMR1 0
+#define IRQ_TMR2 1
+#define IRQ_RTC 2
+#define IRQ_CEC 3
+#define IRQ_SHR_SEM_INBOX_FULL 4
+#define IRQ_SHR_SEM_INBOX_EMPTY 5
+#define IRQ_SHR_SEM_OUTBOX_FULL 6
+#define IRQ_SHR_SEM_OUTBOX_EMPTY 7
+#define IRQ_NVJPEG 8
+#define IRQ_NVDEC 9
+#define IRQ_QUAD_SPI 10
+#define IRQ_DPAUX_INT1 11
+#define IRQ_SATA_RX_STAT 13
+#define IRQ_SDMMC1 14
+#define IRQ_SDMMC2 15
+#define IRQ_VGPIO_INT 16
+#define IRQ_VII2C_INT 17
+#define IRQ_SDMMC3 19
+#define IRQ_USB 20
+#define IRQ_USB2 21
+#define IRQ_SATA_CTL 23
+#define IRQ_PMC_INT 24
+#define IRQ_FC_INT 25
+#define IRQ_APB_DMA_CPU 26
+#define IRQ_ARB_SEM_GNT_COP 28
+#define IRQ_ARB_SEM_GNT_CPU 29
+#define IRQ_SDMMC4 31
+
+/* Secondary interrupt controller ids */
+#define IRQ_GPIO1 32
+#define IRQ_GPIO2 33
+#define IRQ_GPIO3 34
+#define IRQ_GPIO4 35
+#define IRQ_UARTA 36
+#define IRQ_UARTB 37
+#define IRQ_I2C 38
+#define IRQ_USB3_HOST_INT 39
+#define IRQ_USB3_HOST_SMI 40
+#define IRQ_TMR3 41
+#define IRQ_TMR4 42
+#define IRQ_USB3_HOST_PME 43
+#define IRQ_USB3_DEV_HOST 44
+#define IRQ_ACTMON 45
+#define IRQ_UARTC 46
+#define IRQ_THERMAL 48
+#define IRQ_XUSB_PADCTL 49
+#define IRQ_TSEC 50
+#define IRQ_EDP 51
+#define IRQ_I2C5 53
+#define IRQ_GPIO5 55
+#define IRQ_USB3_DEV_SMI 56
+#define IRQ_USB3_DEV_PME 57
+#define IRQ_SE 58
+#define IRQ_SPI1 59
+#define IRQ_APB_DMA_COP 60
+#define IRQ_CLDVFS 62
+#define IRQ_I2C6 63
+
+/* Tertiary interrupt controller ids */
+#define IRQ_HOST1X_SYNCPT_COP 64
+#define IRQ_HOST1X_SYNCPT_CPU 65
+#define IRQ_HOST1X_GEN_COP 66
+#define IRQ_HOST1X_GEN_CPU 67
+#define IRQ_NVENC 68
+#define IRQ_VI 69
+#define IRQ_ISPB 70
+#define IRQ_ISP 71
+#define IRQ_VIC 72
+#define IRQ_DISPLAY 73
+#define IRQ_DISPLAYB 74
+#define IRQ_SOR1 75
+#define IRQ_SOR 76
+#define IRQ_MC 77
+#define IRQ_EMC 78
+#define IRQ_TSECB 80
+#define IRQ_HDA 81
+#define IRQ_SPI2 82
+#define IRQ_SPI3 83
+#define IRQ_I2C2 84
+#define IRQ_PMU_EXT 86
+#define IRQ_GPIO6 87
+#define IRQ_GPIO7 89
+#define IRQ_UARTD 90
+#define IRQ_I2C3 92
+#define IRQ_SPI4 93
+
+/* Quaternary interrupt controller ids */
+#define IRQ_DTV 96
+#define IRQ_PCIE_INT 98
+#define IRQ_PCIE_MSI 99
+#define IRQ_AVP_CACHE 101
+#define IRQ_APE_INT1 102
+#define IRQ_APE_INT0 103
+#define IRQ_APB_DMA_CH0 104
+#define IRQ_APB_DMA_CH1 105
+#define IRQ_APB_DMA_CH2 106
+#define IRQ_APB_DMA_CH3 107
+#define IRQ_APB_DMA_CH4 108
+#define IRQ_APB_DMA_CH5 109
+#define IRQ_APB_DMA_CH6 110
+#define IRQ_APB_DMA_CH7 111
+#define IRQ_APB_DMA_CH8 112
+#define IRQ_APB_DMA_CH9 113
+#define IRQ_APB_DMA_CH10 114
+#define IRQ_APB_DMA_CH11 115
+#define IRQ_APB_DMA_CH12 116
+#define IRQ_APB_DMA_CH13 117
+#define IRQ_APB_DMA_CH14 118
+#define IRQ_APB_DMA_CH15 119
+#define IRQ_I2C4 120
+#define IRQ_TMR5 121
+#define IRQ_WDT_CPU 123
+#define IRQ_WDT_AVP 124
+#define IRQ_GPIO8 125
+#define IRQ_CAR 126
+
+/* Quinary interrupt controller ids */
+#define IRQ_APB_DMA_CH16 128
+#define IRQ_APB_DMA_CH17 129
+#define IRQ_APB_DMA_CH18 130
+#define IRQ_APB_DMA_CH19 131
+#define IRQ_APB_DMA_CH20 132
+#define IRQ_APB_DMA_CH21 133
+#define IRQ_APB_DMA_CH22 134
+#define IRQ_APB_DMA_CH23 135
+#define IRQ_APB_DMA_CH24 136
+#define IRQ_APB_DMA_CH25 137
+#define IRQ_APB_DMA_CH26 138
+#define IRQ_APB_DMA_CH27 139
+#define IRQ_APB_DMA_CH28 140
+#define IRQ_APB_DMA_CH29 141
+#define IRQ_APB_DMA_CH30 142
+#define IRQ_APB_DMA_CH31 143
+#define IRQ_CPU0_PMU_INTR 144
+#define IRQ_CPU1_PMU_INTR 145
+#define IRQ_CPU2_PMU_INTR 146
+#define IRQ_CPU3_PMU_INTR 147
+#define IRQ_SDMMC1_SYS 148
+#define IRQ_SDMMC2_SYS 149
+#define IRQ_SDMMC3_SYS 150
+#define IRQ_SDMMC4_SYS 151
+#define IRQ_TMR6 152
+#define IRQ_TMR7 153
+#define IRQ_TMR8 154
+#define IRQ_TMR9 155
+#define IRQ_TMR0 156
+#define IRQ_GPU_STALL 157
+#define IRQ_GPU_NONSTALL 158
+#define IRQ_DPAUX 159
+
+/* Senary interrupt controller ids */
+#define IRQ_MPCORE_AXIERRIRQ 160
+#define IRQ_MPCORE_INTERRIRQ 161
+#define IRQ_EVENT_GPIO_A 162
+#define IRQ_EVENT_GPIO_B 163
+#define IRQ_EVENT_GPIO_C 164
+#define IRQ_FLOW_RSM_CPU 168
+#define IRQ_FLOW_RSM_COP 169
+#define IRQ_TMR_SHARED 170
+#define IRQ_MPCORE_CTIIRQ0 171
+#define IRQ_MPCORE_CTIIRQ1 172
+#define IRQ_MPCORE_CTIIRQ2 173
+#define IRQ_MPCORE_CTIIRQ3 174
+#define IRQ_MSELECT_ERROR 175
+#define IRQ_TMR10 176
+#define IRQ_TMR11 177
+#define IRQ_TMR12 178
+#define IRQ_TMR13 179
+
+typedef int (*irq_handler_t)(u32 irq, void *data);
+
+typedef enum _irq_status_t
+{
+	IRQ_NONE    = 0,
+	IRQ_HANDLED = 1,
+	IRQ_ERROR   = 2,
+
+	IRQ_ENABLED            = 0,
+	IRQ_NO_SLOTS_AVAILABLE = 1,
+	IRQ_ALREADY_REGISTERED = 2
+} irq_status_t;
+
+typedef enum _irq_flags_t
+{
+	IRQ_FLAG_NONE        = 0,
+	IRQ_FLAG_ONE_OFF     = (1 << 0),
+	IRQ_FLAG_REPLACEABLE = (1 << 1)
+} irq_flags_t;
+
+void irq_end();
+void irq_free(u32 irq);
+void irq_wait_event();
+void irq_disable_wait_event();
+irq_status_t irq_request(u32 irq, irq_handler_t handler, void *data, irq_flags_t flags);
+
+#endif

bdk/soc/kfuse.c

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <soc/kfuse.h>
+#include <soc/clock.h>
+#include <soc/t210.h>
+
+int kfuse_wait_ready()
+{
+	// Wait for KFUSE to finish init and verification of data.
+	while (!(KFUSE(KFUSE_STATE) & KFUSE_STATE_DONE))
+		;
+
+	if (!(KFUSE(KFUSE_STATE) & KFUSE_STATE_CRCPASS))
+		return 0;
+
+	return 1;
+}
+
+int kfuse_read(u32 *buf)
+{
+	int res = 0;
+
+	clock_enable_kfuse();
+
+	if (!kfuse_wait_ready())
+		goto out;
+
+	KFUSE(KFUSE_KEYADDR) = KFUSE_KEYADDR_AUTOINC;
+	for (int i = 0; i < KFUSE_NUM_WORDS; i++)
+		buf[i] = KFUSE(KFUSE_KEYS);
+
+	res = 1;
+
+out:
+	clock_disable_kfuse();
+	return res;
+}

bdk/soc/kfuse.h

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _KFUSE_H_
+#define _KFUSE_H_
+
+#include <utils/types.h>
+
+#define KFUSE_STATE_SOFTRESET      (1 << 31)
+#define KFUSE_STATE_STOP           (1 << 25)
+#define KFUSE_STATE_RESTART        (1 << 24)
+#define KFUSE_STATE_CRCPASS        (1 << 17)
+#define KFUSE_STATE_DONE           (1 << 16)
+#define KFUSE_STATE_ERRBLOCK_MASK  0x3F00
+#define KFUSE_STATE_ERRBLOCK_SHIFT 8
+#define KFUSE_STATE_CURBLOCK_MASK  0x3F
+
+#define KFUSE_KEYADDR_AUTOINC (1<<16)
+
+#define KFUSE_STATE 0x80
+#define KFUSE_KEYADDR 0x88
+#define KFUSE_KEYS 0x8C
+
+#define KFUSE_NUM_WORDS 144
+
+int kfuse_wait_ready();
+int kfuse_read(u32 *buf);
+
+#endif

bdk/soc/pinmux.c

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <soc/pinmux.h>
+#include <soc/t210.h>
+
+void pinmux_config_uart(u32 idx)
+{
+	PINMUX_AUX(PINMUX_AUX_UARTX_TX(idx)) = 0;
+	PINMUX_AUX(PINMUX_AUX_UARTX_RX(idx)) = PINMUX_INPUT_ENABLE | PINMUX_PULL_UP;
+	PINMUX_AUX(PINMUX_AUX_UARTX_RTS(idx)) = 0;
+	PINMUX_AUX(PINMUX_AUX_UARTX_CTS(idx)) = PINMUX_INPUT_ENABLE | PINMUX_PULL_DOWN;
+}
+
+void pinmux_config_i2c(u32 idx)
+{
+	PINMUX_AUX(PINMUX_AUX_X_I2C_SCL(idx)) = PINMUX_INPUT_ENABLE;
+	PINMUX_AUX(PINMUX_AUX_X_I2C_SDA(idx)) = PINMUX_INPUT_ENABLE;
+}

bdk/soc/pinmux.h

@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _PINMUX_H_
+#define _PINMUX_H_
+
+#include <utils/types.h>
+
+/*! APB MISC registers. */
+#define APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL 0x8D4
+#define APB_MISC_GP_SDMMC3_CLK_LPBK_CONTROL 0x8D8
+#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL   0xA98
+#define APB_MISC_GP_VGPIO_GPIO_MUX_SEL      0xB74
+
+/*! Pinmux registers. */
+#define PINMUX_AUX_SDMMC1_CLK      0x00
+#define PINMUX_AUX_SDMMC1_CMD      0x04
+#define PINMUX_AUX_SDMMC1_DAT3     0x08
+#define PINMUX_AUX_SDMMC1_DAT2     0x0C
+#define PINMUX_AUX_SDMMC1_DAT1     0x10
+#define PINMUX_AUX_SDMMC1_DAT0     0x14
+#define PINMUX_AUX_SDMMC3_CLK      0x1C
+#define PINMUX_AUX_SDMMC3_CMD      0x20
+#define PINMUX_AUX_SDMMC3_DAT0     0x24
+#define PINMUX_AUX_SDMMC3_DAT1     0x28
+#define PINMUX_AUX_SDMMC3_DAT2     0x2C
+#define PINMUX_AUX_SDMMC3_DAT3     0x30
+#define PINMUX_AUX_SATA_LED_ACTIVE 0x4C
+#define PINMUX_AUX_DMIC3_CLK       0xB4
+#define PINMUX_AUX_DMIC3_DAT       0xB8
+#define PINMUX_AUX_CAM_I2C_SCL     0xD4
+#define PINMUX_AUX_CAM_I2C_SDA     0xD8
+#define PINMUX_AUX_UART2_TX        0xF4
+#define PINMUX_AUX_UART3_TX        0x104
+#define PINMUX_AUX_DAP4_DIN        0x148
+#define PINMUX_AUX_DAP4_SCLK       0x150
+#define PINMUX_AUX_GPIO_X1_AUD     0x18C
+#define PINMUX_AUX_GPIO_X3_AUD     0x190
+#define PINMUX_AUX_SPDIF_IN        0x1A4
+#define PINMUX_AUX_USB_VBUS_EN0    0x1A8
+#define PINMUX_AUX_USB_VBUS_EN1    0x1AC
+#define PINMUX_AUX_WIFI_EN         0x1B4
+#define PINMUX_AUX_WIFI_RST        0x1B8
+#define PINMUX_AUX_AP_WAKE_NFC     0x1CC
+#define PINMUX_AUX_NFC_EN          0x1D0
+#define PINMUX_AUX_NFC_INT         0x1D4
+#define PINMUX_AUX_CAM1_PWDN       0x1EC
+#define PINMUX_AUX_CAM2_PWDN       0x1F0
+#define PINMUX_AUX_LCD_BL_PWM      0x1FC
+#define PINMUX_AUX_LCD_BL_EN       0x200
+#define PINMUX_AUX_LCD_RST         0x204
+#define PINMUX_AUX_LCD_GPIO1       0x208
+#define PINMUX_AUX_LCD_GPIO2       0x20C
+#define PINMUX_AUX_TOUCH_INT       0x220
+#define PINMUX_AUX_MOTION_INT      0x224
+#define PINMUX_AUX_BUTTON_HOME     0x240
+#define PINMUX_AUX_GPIO_PE6        0x248
+#define PINMUX_AUX_GPIO_PH6        0x250
+#define PINMUX_AUX_GPIO_PK3        0x260
+#define PINMUX_AUX_GPIO_PZ1        0x280
+/*! 0:UART-A, 1:UART-B, 3:UART-C, 3:UART-D */
+#define PINMUX_AUX_UARTX_TX(x)  (0xE4 + 0x10 * (x))
+#define PINMUX_AUX_UARTX_RX(x)  (0xE8 + 0x10 * (x))
+#define PINMUX_AUX_UARTX_RTS(x) (0xEC + 0x10 * (x))
+#define PINMUX_AUX_UARTX_CTS(x) (0xF0 + 0x10 * (x))
+/*! 0:GEN1, 1:GEN2, 2:GEN3, 3:CAM, 4:PWR */
+#define PINMUX_AUX_X_I2C_SCL(x) (0xBC + 8 * (x))
+#define PINMUX_AUX_X_I2C_SDA(x) (0xC0 + 8 * (x))
+
+#define PINMUX_FUNC_MASK    (3 << 0)
+
+#define PINMUX_PULL_MASK    (3 << 2)
+#define PINMUX_PULL_NONE    (0 << 2)
+#define PINMUX_PULL_DOWN    (1 << 2)
+#define PINMUX_PULL_UP      (2 << 2)
+
+#define PINMUX_TRISTATE     (1 << 4)
+#define PINMUX_PARKED       (1 << 5)
+#define PINMUX_INPUT_ENABLE (1 << 6)
+#define PINMUX_LOCK         (1 << 7)
+#define PINMUX_LPDR         (1 << 8)
+#define PINMUX_HSM          (1 << 9)
+
+#define PINMUX_IO_HV        (1 << 10)
+#define PINMUX_OPEN_DRAIN   (1 << 11)
+#define PINMUX_SCHMT        (1 << 12)
+
+#define PINMUX_DRIVE_1X     (0 << 13)
+#define PINMUX_DRIVE_2X     (1 << 13)
+#define PINMUX_DRIVE_3X     (2 << 13)
+#define PINMUX_DRIVE_4X     (3 << 13)
+
+void pinmux_config_uart(u32 idx);
+void pinmux_config_i2c(u32 idx);
+
+#endif

bdk/soc/pmc.h

@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2018 naehrwert
+ * Copyright (c) 2018 st4rk
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef _PMC_H_
+#define _PMC_H_
+
+/*! PMC registers. */
+#define APBDEV_PMC_CNTRL 0x0
+#define  PMC_CNTRL_MAIN_RST (1 << 4)
+#define APBDEV_PMC_SEC_DISABLE 0x4
+#define APBDEV_PMC_PWRGATE_TOGGLE 0x30
+#define APBDEV_PMC_PWRGATE_STATUS 0x38
+#define APBDEV_PMC_NO_IOPOWER 0x44
+#define  PMC_NO_IOPOWER_GPIO_IO_EN   (1 << 21)
+#define  PMC_NO_IOPOWER_AUDIO_HV     (1 << 18)
+#define  PMC_NO_IOPOWER_SDMMC1_IO_EN (1 << 12)
+#define APBDEV_PMC_SCRATCH0 0x50
+#define  PMC_SCRATCH0_MODE_RECOVERY (1 << 31)
+#define  PMC_SCRATCH0_MODE_FASTBOOT (1 << 30)
+#define  PMC_SCRATCH0_MODE_PAYLOAD  (1 << 29)
+#define  PMC_SCRATCH0_MODE_RCM      (1 << 1)
+#define  PMC_SCRATCH0_MODE_WARMBOOT (1 << 0)
+#define APBDEV_PMC_SCRATCH1 0x54
+#define APBDEV_PMC_SCRATCH20 0xA0
+#define APBDEV_PMC_PWR_DET_VAL 0xE4
+#define  PMC_PWR_DET_GPIO_IO_EN   (1 << 21)
+#define  PMC_PWR_DET_AUDIO_HV     (1 << 18)
+#define  PMC_PWR_DET_SDMMC1_IO_EN (1 << 12)
+#define APBDEV_PMC_DDR_PWR 0xE8
+#define APBDEV_PMC_USB_AO 0xF0
+#define APBDEV_PMC_CRYPTO_OP 0xF4
+#define  PMC_CRYPTO_OP_SE_ENABLE  0
+#define  PMC_CRYPTO_OP_SE_DISABLE 1
+#define APBDEV_PMC_SCRATCH33 0x120
+#define APBDEV_PMC_SCRATCH40 0x13C
+#define APBDEV_PMC_OSC_EDPD_OVER 0x1A4
+#define  PMC_OSC_EDPD_OVER_OSC_CTRL_OVER 0x400000
+#define APBDEV_PMC_CLK_OUT_CNTRL 0x1A8
+#define  PMC_CLK_OUT_CNTRL_CLK1_FORCE_EN (1 << 2)
+#define APBDEV_PMC_RST_STATUS 0x1B4
+#define APBDEV_PMC_IO_DPD_REQ 0x1B8
+#define APBDEV_PMC_IO_DPD2_REQ 0x1C0
+#define APBDEV_PMC_VDDP_SEL 0x1CC
+#define APBDEV_PMC_DDR_CFG 0x1D0
+#define APBDEV_PMC_SCRATCH45 0x234
+#define APBDEV_PMC_SCRATCH46 0x238
+#define APBDEV_PMC_SCRATCH49 0x244
+#define APBDEV_PMC_TSC_MULT 0x2B4
+#define APBDEV_PMC_SEC_DISABLE2 0x2C4
+#define APBDEV_PMC_WEAK_BIAS 0x2C8
+#define APBDEV_PMC_REG_SHORT 0x2CC
+#define APBDEV_PMC_SEC_DISABLE3 0x2D8
+#define APBDEV_PMC_SECURE_SCRATCH21 0x334
+#define  PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT 0x10
+#define APBDEV_PMC_SECURE_SCRATCH32 0x360
+#define APBDEV_PMC_SECURE_SCRATCH49 0x3A4
+#define APBDEV_PMC_CNTRL2 0x440
+#define  PMC_CNTRL2_HOLD_CKE_LOW_EN 0x1000
+#define APBDEV_PMC_IO_DPD3_REQ 0x45C
+#define APBDEV_PMC_IO_DPD4_REQ 0x464
+#define APBDEV_PMC_UTMIP_PAD_CFG1 0x4C4
+#define APBDEV_PMC_UTMIP_PAD_CFG3 0x4CC
+#define APBDEV_PMC_DDR_CNTRL 0x4E4
+#define APBDEV_PMC_SEC_DISABLE4 0x5B0
+#define APBDEV_PMC_SEC_DISABLE5 0x5B4
+#define APBDEV_PMC_SEC_DISABLE6 0x5B8
+#define APBDEV_PMC_SEC_DISABLE7 0x5BC
+#define APBDEV_PMC_SEC_DISABLE8 0x5C0
+#define APBDEV_PMC_SCRATCH188 0x810
+#define APBDEV_PMC_SCRATCH190 0x818
+#define APBDEV_PMC_SCRATCH200 0x840
+
+#endif

bdk/soc/pmc_lp0_t210.h

@@ -0,0 +1,564 @@
+/*
+ * Copyright (c) 2010-2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _TEGRA210_PMC_H_
+#define _TEGRA210_PMC_H_
+
+#include <utils/types.h>
+
+struct tegra_pmc_regs
+{
+	u32 cntrl;
+	u32 sec_disable;
+	u32 pmc_swrst;
+	u32 wake_mask;
+	u32 wake_lvl;
+	u32 wake_status;
+	u32 sw_wake_status;
+	u32 dpd_pads_oride;
+	u32 dpd_sample;
+	u32 dpd_enable;
+	u32 pwrgate_timer_off;
+	u32 clamp_status;
+	u32 pwrgate_toggle;
+	u32 remove_clamping_cmd;
+	u32 pwrgate_status;
+	u32 pwrgood_timer;
+	u32 blink_timer;
+	u32 no_iopower;
+	u32 pwr_det;
+	u32 pwr_det_latch;
+	u32 scratch0;
+	u32 scratch1;
+	u32 scratch2;
+	u32 scratch3;
+	u32 scratch4;
+	u32 scratch5;
+	u32 scratch6;
+	u32 scratch7;
+	u32 scratch8;
+	u32 scratch9;
+	u32 scratch10;
+	u32 scratch11;
+	u32 scratch12;
+	u32 scratch13;
+	u32 scratch14;
+	u32 scratch15;
+	u32 scratch16;
+	u32 scratch17;
+	u32 scratch18;
+	u32 scratch19;
+	u32 odmdata;
+	u32 scratch21;
+	u32 scratch22;
+	u32 scratch23;
+	u32 secure_scratch0;
+	u32 secure_scratch1;
+	u32 secure_scratch2;
+	u32 secure_scratch3;
+	u32 secure_scratch4;
+	u32 secure_scratch5;
+	u32 cpupwrgood_timer;
+	u32 cpupwroff_timer;
+	u32 pg_mask;
+	u32 pg_mask_1;
+	u32 auto_wake_lvl;
+	u32 auto_wake_lvl_mask;
+	u32 wake_delay;
+	u32 pwr_det_val;
+	u32 ddr_pwr;
+	u32 usb_debounce_del;
+	u32 usb_a0;
+	u32 crypto_op;
+	u32 pllp_wb0_override;
+	u32 scratch24;
+	u32 scratch25;
+	u32 scratch26;
+	u32 scratch27;
+	u32 scratch28;
+	u32 scratch29;
+	u32 scratch30;
+	u32 scratch31;
+	u32 scratch32;
+	u32 scratch33;
+	u32 scratch34;
+	u32 scratch35;
+	u32 scratch36;
+	u32 scratch37;
+	u32 scratch38;
+	u32 scratch39;
+	u32 scratch40;
+	u32 scratch41;
+	u32 scratch42;
+	u32 bondout_mirror[3];
+	u32 sys_33v_en;
+	u32 bondout_mirror_access;
+	u32 gate;
+	u32 wake2_mask;
+	u32 wake2_lvl;
+	u32 wake2_status;
+	u32 sw_wake2_status;
+	u32 auto_wake2_lvl_mask;
+	u32 pg_mask_2;
+	u32 pg_mask_ce1;
+	u32 pg_mask_ce2;
+	u32 pg_mask_ce3;
+	u32 pwrgate_timer_ce[7];
+	u32 pcx_edpd_cntrl;
+	u32 osc_edpd_over;
+	u32 clk_out_cntrl;
+	u32 sata_pwrgt;
+	u32 sensor_ctrl;
+	u32 rst_status;
+	u32 io_dpd_req;
+	u32 io_dpd_status;
+	u32 io_dpd2_req;
+	u32 io_dpd2_status;
+	u32 sel_dpd_tim;
+	u32 vddp_sel;
+	u32 ddr_cfg;
+	u32 e_no_vttgen;
+	u8 _rsv0[4];
+	u32 pllm_wb0_override_freq;
+	u32 test_pwrgate;
+	u32 pwrgate_timer_mult;
+	u32 dis_sel_dpd;
+	u32 utmip_uhsic_triggers;
+	u32 utmip_uhsic_saved_state;
+	u32 utmip_pad_cfg;
+	u32 utmip_term_pad_cfg;
+	u32 utmip_uhsic_sleep_cfg;
+	u32 utmip_uhsic_sleepwalk_cfg;
+	u32 utmip_sleepwalk_p[3];
+	u32 uhsic_sleepwalk_p0;
+	u32 utmip_uhsic_status;
+	u32 utmip_uhsic_fake;
+	u32 bondout_mirror3[5 - 3];
+	u32 secure_scratch6;
+	u32 secure_scratch7;
+	u32 scratch43;
+	u32 scratch44;
+	u32 scratch45;
+	u32 scratch46;
+	u32 scratch47;
+	u32 scratch48;
+	u32 scratch49;
+	u32 scratch50;
+	u32 scratch51;
+	u32 scratch52;
+	u32 scratch53;
+	u32 scratch54;
+	u32 scratch55;
+	u32 scratch0_eco;
+	u32 por_dpd_ctrl;
+	u32 scratch2_eco;
+	u32 utmip_uhsic_line_wakeup;
+	u32 utmip_bias_master_cntrl;
+	u32 utmip_master_config;
+	u32 td_pwrgate_inter_part_timer;
+	u32 utmip_uhsic2_triggers;
+	u32 utmip_uhsic2_saved_state;
+	u32 utmip_uhsic2_sleep_cfg;
+	u32 utmip_uhsic2_sleepwalk_cfg;
+	u32 uhsic2_sleepwalk_p1;
+	u32 utmip_uhsic2_status;
+	u32 utmip_uhsic2_fake;
+	u32 utmip_uhsic2_line_wakeup;
+	u32 utmip_master2_config;
+	u32 utmip_uhsic_rpd_cfg;
+	u32 pg_mask_ce0;
+	u32 pg_mask3[5 - 3];
+	u32 pllm_wb0_override2;
+	u32 tsc_mult;
+	u32 cpu_vsense_override;
+	u32 glb_amap_cfg;
+	u32 sticky_bits;
+	u32 sec_disable2;
+	u32 weak_bias;
+	u32 reg_short;
+	u32 pg_mask_andor;
+	u8 _rsv1[0x2c];
+	u32 secure_scratch8;	/* offset 0x300 */
+	u32 secure_scratch9;
+	u32 secure_scratch10;
+	u32 secure_scratch11;
+	u32 secure_scratch12;
+	u32 secure_scratch13;
+	u32 secure_scratch14;
+	u32 secure_scratch15;
+	u32 secure_scratch16;
+	u32 secure_scratch17;
+	u32 secure_scratch18;
+	u32 secure_scratch19;
+	u32 secure_scratch20;
+	u32 secure_scratch21;
+	u32 secure_scratch22;
+	u32 secure_scratch23;
+	u32 secure_scratch24;
+	u32 secure_scratch25;
+	u32 secure_scratch26;
+	u32 secure_scratch27;
+	u32 secure_scratch28;
+	u32 secure_scratch29;
+	u32 secure_scratch30;
+	u32 secure_scratch31;
+	u32 secure_scratch32;
+	u32 secure_scratch33;
+	u32 secure_scratch34;
+	u32 secure_scratch35;
+	u32 secure_scratch36;
+	u32 secure_scratch37;
+	u32 secure_scratch38;
+	u32 secure_scratch39;
+	u32 secure_scratch40;
+	u32 secure_scratch41;
+	u32 secure_scratch42;
+	u32 secure_scratch43;
+	u32 secure_scratch44;
+	u32 secure_scratch45;
+	u32 secure_scratch46;
+	u32 secure_scratch47;
+	u32 secure_scratch48;
+	u32 secure_scratch49;
+	u32 secure_scratch50;
+	u32 secure_scratch51;
+	u32 secure_scratch52;
+	u32 secure_scratch53;
+	u32 secure_scratch54;
+	u32 secure_scratch55;
+	u32 secure_scratch56;
+	u32 secure_scratch57;
+	u32 secure_scratch58;
+	u32 secure_scratch59;
+	u32 secure_scratch60;
+	u32 secure_scratch61;
+	u32 secure_scratch62;
+	u32 secure_scratch63;
+	u32 secure_scratch64;
+	u32 secure_scratch65;
+	u32 secure_scratch66;
+	u32 secure_scratch67;
+	u32 secure_scratch68;
+	u32 secure_scratch69;
+	u32 secure_scratch70;
+	u32 secure_scratch71;
+	u32 secure_scratch72;
+	u32 secure_scratch73;
+	u32 secure_scratch74;
+	u32 secure_scratch75;
+	u32 secure_scratch76;
+	u32 secure_scratch77;
+	u32 secure_scratch78;
+	u32 secure_scratch79;
+	u32 _rsv0x420[8];
+	u32 cntrl2;			/* 0x440 */
+	u32 _rsv0x444[2];
+	u32 event_counter;	/* 0x44C */
+	u32 fuse_control;
+	u32 scratch1_eco;
+	u32 _rsv0x458[1];
+	u32 io_dpd3_req;	/* 0x45C */
+	u32 io_dpd3_status;
+	u32 io_dpd4_req;
+	u32 io_dpd4_status;
+	u32 _rsv0x46C[30];
+	u32 ddr_cntrl;		/* 0x4E4 */
+	u32 _rsv0x4E8[70];
+	u32 scratch56;		/* 0x600 */
+	u32 scratch57;
+	u32 scratch58;
+	u32 scratch59;
+	u32 scratch60;
+	u32 scratch61;
+	u32 scratch62;
+	u32 scratch63;
+	u32 scratch64;
+	u32 scratch65;
+	u32 scratch66;
+	u32 scratch67;
+	u32 scratch68;
+	u32 scratch69;
+	u32 scratch70;
+	u32 scratch71;
+	u32 scratch72;
+	u32 scratch73;
+	u32 scratch74;
+	u32 scratch75;
+	u32 scratch76;
+	u32 scratch77;
+	u32 scratch78;
+	u32 scratch79;
+	u32 scratch80;
+	u32 scratch81;
+	u32 scratch82;
+	u32 scratch83;
+	u32 scratch84;
+	u32 scratch85;
+	u32 scratch86;
+	u32 scratch87;
+	u32 scratch88;
+	u32 scratch89;
+	u32 scratch90;
+	u32 scratch91;
+	u32 scratch92;
+	u32 scratch93;
+	u32 scratch94;
+	u32 scratch95;
+	u32 scratch96;
+	u32 scratch97;
+	u32 scratch98;
+	u32 scratch99;
+	u32 scratch100;
+	u32 scratch101;
+	u32 scratch102;
+	u32 scratch103;
+	u32 scratch104;
+	u32 scratch105;
+	u32 scratch106;
+	u32 scratch107;
+	u32 scratch108;
+	u32 scratch109;
+	u32 scratch110;
+	u32 scratch111;
+	u32 scratch112;
+	u32 scratch113;
+	u32 scratch114;
+	u32 scratch115;
+	u32 scratch116;
+	u32 scratch117;
+	u32 scratch118;
+	u32 scratch119;
+	u32 scratch120;		/* 0x700 */
+	u32 scratch121;
+	u32 scratch122;
+	u32 scratch123;
+	u32 scratch124;
+	u32 scratch125;
+	u32 scratch126;
+	u32 scratch127;
+	u32 scratch128;
+	u32 scratch129;
+	u32 scratch130;
+	u32 scratch131;
+	u32 scratch132;
+	u32 scratch133;
+	u32 scratch134;
+	u32 scratch135;
+	u32 scratch136;
+	u32 scratch137;
+	u32 scratch138;
+	u32 scratch139;
+	u32 scratch140;
+	u32 scratch141;
+	u32 scratch142;
+	u32 scratch143;
+	u32 scratch144;
+	u32 scratch145;
+	u32 scratch146;
+	u32 scratch147;
+	u32 scratch148;
+	u32 scratch149;
+	u32 scratch150;
+	u32 scratch151;
+	u32 scratch152;
+	u32 scratch153;
+	u32 scratch154;
+	u32 scratch155;
+	u32 scratch156;
+	u32 scratch157;
+	u32 scratch158;
+	u32 scratch159;
+	u32 scratch160;
+	u32 scratch161;
+	u32 scratch162;
+	u32 scratch163;
+	u32 scratch164;
+	u32 scratch165;
+	u32 scratch166;
+	u32 scratch167;
+	u32 scratch168;
+	u32 scratch169;
+	u32 scratch170;
+	u32 scratch171;
+	u32 scratch172;
+	u32 scratch173;
+	u32 scratch174;
+	u32 scratch175;
+	u32 scratch176;
+	u32 scratch177;
+	u32 scratch178;
+	u32 scratch179;
+	u32 scratch180;
+	u32 scratch181;
+	u32 scratch182;
+	u32 scratch183;
+	u32 scratch184;
+	u32 scratch185;
+	u32 scratch186;
+	u32 scratch187;
+	u32 scratch188;
+	u32 scratch189;
+	u32 scratch190;
+	u32 scratch191;
+	u32 scratch192;
+	u32 scratch193;
+	u32 scratch194;
+	u32 scratch195;
+	u32 scratch196;
+	u32 scratch197;
+	u32 scratch198;
+	u32 scratch199;
+	u32 scratch200;
+	u32 scratch201;
+	u32 scratch202;
+	u32 scratch203;
+	u32 scratch204;
+	u32 scratch205;
+	u32 scratch206;
+	u32 scratch207;
+	u32 scratch208;
+	u32 scratch209;
+	u32 scratch210;
+	u32 scratch211;
+	u32 scratch212;
+	u32 scratch213;
+	u32 scratch214;
+	u32 scratch215;
+	u32 scratch216;
+	u32 scratch217;
+	u32 scratch218;
+	u32 scratch219;
+	u32 scratch220;
+	u32 scratch221;
+	u32 scratch222;
+	u32 scratch223;
+	u32 scratch224;
+	u32 scratch225;
+	u32 scratch226;
+	u32 scratch227;
+	u32 scratch228;
+	u32 scratch229;
+	u32 scratch230;
+	u32 scratch231;
+	u32 scratch232;
+	u32 scratch233;
+	u32 scratch234;
+	u32 scratch235;
+	u32 scratch236;
+	u32 scratch237;
+	u32 scratch238;
+	u32 scratch239;
+	u32 scratch240;
+	u32 scratch241;
+	u32 scratch242;
+	u32 scratch243;
+	u32 scratch244;
+	u32 scratch245;
+	u32 scratch246;
+	u32 scratch247;
+	u32 scratch248;
+	u32 scratch249;
+	u32 scratch250;
+	u32 scratch251;
+	u32 scratch252;
+	u32 scratch253;
+	u32 scratch254;
+	u32 scratch255;
+	u32 scratch256;
+	u32 scratch257;
+	u32 scratch258;
+	u32 scratch259;
+	u32 scratch260;
+	u32 scratch261;
+	u32 scratch262;
+	u32 scratch263;
+	u32 scratch264;
+	u32 scratch265;
+	u32 scratch266;
+	u32 scratch267;
+	u32 scratch268;
+	u32 scratch269;
+	u32 scratch270;
+	u32 scratch271;
+	u32 scratch272;
+	u32 scratch273;
+	u32 scratch274;
+	u32 scratch275;
+	u32 scratch276;
+	u32 scratch277;
+	u32 scratch278;
+	u32 scratch279;
+	u32 scratch280;
+	u32 scratch281;
+	u32 scratch282;
+	u32 scratch283;
+	u32 scratch284;
+	u32 scratch285;
+	u32 scratch286;
+	u32 scratch287;
+	u32 scratch288;
+	u32 scratch289;
+	u32 scratch290;
+	u32 scratch291;
+	u32 scratch292;
+	u32 scratch293;
+	u32 scratch294;
+	u32 scratch295;
+	u32 scratch296;
+	u32 scratch297;
+	u32 scratch298;
+	u32 scratch299;			/* 0x9CC */
+	u32 _rsv0x9D0[50];
+	u32 secure_scratch80;	/* 0xa98 */
+	u32 secure_scratch81;
+	u32 secure_scratch82;
+	u32 secure_scratch83;
+	u32 secure_scratch84;
+	u32 secure_scratch85;
+	u32 secure_scratch86;
+	u32 secure_scratch87;
+	u32 secure_scratch88;
+	u32 secure_scratch89;
+	u32 secure_scratch90;
+	u32 secure_scratch91;
+	u32 secure_scratch92;
+	u32 secure_scratch93;
+	u32 secure_scratch94;
+	u32 secure_scratch95;
+	u32 secure_scratch96;
+	u32 secure_scratch97;
+	u32 secure_scratch98;
+	u32 secure_scratch99;
+	u32 secure_scratch100;
+	u32 secure_scratch101;
+	u32 secure_scratch102;
+	u32 secure_scratch103;
+	u32 secure_scratch104;
+	u32 secure_scratch105;
+	u32 secure_scratch106;
+	u32 secure_scratch107;
+	u32 secure_scratch108;
+	u32 secure_scratch109;
+	u32 secure_scratch110;
+	u32 secure_scratch111;
+	u32 secure_scratch112;
+	u32 secure_scratch113;
+	u32 secure_scratch114;
+	u32 secure_scratch115;
+	u32 secure_scratch116;
+	u32 secure_scratch117;
+	u32 secure_scratch118;
+	u32 secure_scratch119;
+};
+
+#endif	/* _TEGRA210_PMC_H_ */

bdk/soc/t210.h

@@ -0,0 +1,288 @@
+/*
+* Copyright (c) 2018 naehrwert
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms and conditions of the GNU General Public License,
+* version 2, as published by the Free Software Foundation.
+*
+* This program is distributed in the hope it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef _T210_H_
+#define _T210_H_
+
+#include <utils/types.h>
+
+#define BOOTROM_BASE 0x100000
+#define IRAM_BASE 0x40000000
+#define HOST1X_BASE 0x50000000
+#define BPMP_CACHE_BASE 0x50040000
+#define DISPLAY_A_BASE 0x54200000
+#define DSI_BASE 0x54300000
+#define VIC_BASE 0x54340000
+#define TSEC_BASE 0x54500000
+#define SOR1_BASE 0x54580000
+#define ICTLR_BASE 0x60004000
+#define TMR_BASE 0x60005000
+#define CLOCK_BASE 0x60006000
+#define FLOW_CTLR_BASE 0x60007000
+#define AHBDMA_BASE 0x60008000
+#define SYSREG_BASE 0x6000C000
+#define SB_BASE (SYSREG_BASE + 0x200)
+#define GPIO_BASE 0x6000D000
+#define GPIO_1_BASE (GPIO_BASE)
+#define GPIO_2_BASE (GPIO_BASE + 0x100)
+#define GPIO_3_BASE (GPIO_BASE + 0x200)
+#define GPIO_4_BASE (GPIO_BASE + 0x300)
+#define GPIO_5_BASE (GPIO_BASE + 0x400)
+#define GPIO_6_BASE (GPIO_BASE + 0x500)
+#define GPIO_7_BASE (GPIO_BASE + 0x600)
+#define GPIO_8_BASE (GPIO_BASE + 0x700)
+#define EXCP_VEC_BASE 0x6000F000
+#define IPATCH_BASE 0x6001DC00
+#define APBDMA_BASE 0x60020000
+#define APB_MISC_BASE 0x70000000
+#define PINMUX_AUX_BASE 0x70003000
+#define UART_BASE 0x70006000
+#define PWM_BASE 0x7000A000
+#define RTC_BASE 0x7000E000
+#define PMC_BASE 0x7000E400
+#define SYSCTR0_BASE 0x700F0000
+#define FUSE_BASE 0x7000F800
+#define KFUSE_BASE 0x7000FC00
+#define SE_BASE 0x70012000
+#define MC_BASE 0x70019000
+#define EMC_BASE 0x7001B000
+#define EMC0_BASE 0x7001E000
+#define EMC1_BASE 0x7001F000
+#define MIPI_CAL_BASE 0x700E3000
+#define CL_DVFS_BASE 0x70110000
+#define I2S_BASE 0x702D1000
+#define ADMA_BASE 0x702E2000
+#define TZRAM_BASE 0x7C010000
+#define USB_BASE 0x7D000000
+#define USB_OTG_BASE USB_BASE
+#define USB1_BASE 0x7D004000
+
+#define _REG(base, off) *(vu32 *)((base) + (off))
+
+#define HOST1X(off) _REG(HOST1X_BASE, off)
+#define BPMP_CACHE_CTRL(off) _REG(BPMP_CACHE_BASE, off)
+#define DISPLAY_A(off) _REG(DISPLAY_A_BASE, off)
+#define DSI(off) _REG(DSI_BASE, off)
+#define VIC(off) _REG(VIC_BASE, off)
+#define TSEC(off) _REG(TSEC_BASE, off)
+#define SOR1(off) _REG(SOR1_BASE, off)
+#define ICTLR(cidx, off) _REG(ICTLR_BASE + (0x100 * cidx), off)
+#define TMR(off) _REG(TMR_BASE, off)
+#define CLOCK(off) _REG(CLOCK_BASE, off)
+#define FLOW_CTLR(off) _REG(FLOW_CTLR_BASE, off)
+#define SYSREG(off) _REG(SYSREG_BASE, off)
+#define AHB_GIZMO(off) _REG(SYSREG_BASE, off)
+#define SB(off) _REG(SB_BASE, off)
+#define GPIO(off) _REG(GPIO_BASE, off)
+#define GPIO_1(off) _REG(GPIO_1_BASE, off)
+#define GPIO_2(off) _REG(GPIO_2_BASE, off)
+#define GPIO_3(off) _REG(GPIO_3_BASE, off)
+#define GPIO_4(off) _REG(GPIO_4_BASE, off)
+#define GPIO_5(off) _REG(GPIO_5_BASE, off)
+#define GPIO_6(off) _REG(GPIO_6_BASE, off)
+#define GPIO_7(off) _REG(GPIO_7_BASE, off)
+#define GPIO_8(off) _REG(GPIO_8_BASE, off)
+#define EXCP_VEC(off) _REG(EXCP_VEC_BASE, off)
+#define APB_MISC(off) _REG(APB_MISC_BASE, off)
+#define PINMUX_AUX(off) _REG(PINMUX_AUX_BASE, off)
+#define PWM(off) _REG(PWM_BASE, off)
+#define RTC(off) _REG(RTC_BASE, off)
+#define PMC(off) _REG(PMC_BASE, off)
+#define SYSCTR0(off) _REG(SYSCTR0_BASE, off)
+#define FUSE(off) _REG(FUSE_BASE, off)
+#define KFUSE(off) _REG(KFUSE_BASE, off)
+#define SE(off) _REG(SE_BASE, off)
+#define MC(off) _REG(MC_BASE, off)
+#define EMC(off) _REG(EMC_BASE, off)
+#define EMC_CH0(off) _REG(EMC0_BASE, off)
+#define EMC_CH1(off) _REG(EMC1_BASE, off)
+#define MIPI_CAL(off) _REG(MIPI_CAL_BASE, off)
+#define CL_DVFS(off) _REG(CL_DVFS_BASE, off)
+#define I2S(off) _REG(I2S_BASE, off)
+#define ADMA(off) _REG(ADMA_BASE, off)
+#define USB(off) _REG(USB_BASE, off)
+#define USB1(off) _REG(USB1_BASE, off)
+#define TEST_REG(off) _REG(0x0, off)
+
+/* HOST1X registers. */
+#define HOST1X_CH0_SYNC_BASE 0x2100
+#define HOST1X_CH0_SYNC_SYNCPT_9   (HOST1X_CH0_SYNC_BASE + 0xFA4)
+#define HOST1X_CH0_SYNC_SYNCPT_160 (HOST1X_CH0_SYNC_BASE + 0x1200)
+
+/*! EVP registers. */
+#define EVP_CPU_RESET_VECTOR 0x100
+#define EVP_COP_RESET_VECTOR 0x200
+#define EVP_COP_UNDEF_VECTOR 0x204
+#define EVP_COP_SWI_VECTOR 0x208
+#define EVP_COP_PREFETCH_ABORT_VECTOR 0x20C
+#define EVP_COP_DATA_ABORT_VECTOR 0x210
+#define EVP_COP_RSVD_VECTOR 0x214
+#define EVP_COP_IRQ_VECTOR 0x218
+#define EVP_COP_FIQ_VECTOR 0x21C
+#define EVP_COP_IRQ_STS 0x220
+
+/*! Primary Interrupt Controller registers. */
+#define PRI_ICTLR_FIR 0x14
+#define PRI_ICTLR_FIR_SET 0x18
+#define PRI_ICTLR_FIR_CLR 0x1C
+#define PRI_ICTLR_CPU_IER 0x20
+#define PRI_ICTLR_CPU_IER_SET 0x24
+#define PRI_ICTLR_CPU_IER_CLR 0x28
+#define PRI_ICTLR_CPU_IEP_CLASS 0x2C
+#define PRI_ICTLR_COP_IER 0x30
+#define PRI_ICTLR_COP_IER_SET 0x34
+#define PRI_ICTLR_COP_IER_CLR 0x38
+#define PRI_ICTLR_COP_IEP_CLASS 0x3C
+
+/*! AHB Gizmo registers. */
+#define AHB_ARBITRATION_PRIORITY_CTRL 0x8
+#define  ARBITRATION_PRIORITY_CTRL_ENB_FAST_REARBITRATE (1 << 6)
+#define AHB_GIZMO_AHB_MEM 0x10
+#define  AHB_MEM_ENB_FAST_REARBITRATE (1 << 2)
+#define AHB_GIZMO_USB 0x20
+#define  AHB_GIZMO_USB_IMMEDIATE (1 << 18)
+#define AHB_AHB_MEM_PREFETCH_CFG1 0xF0
+#define  MEM_PREFETCH_ENABLE (1 << 31)
+#define  MEM_PREFETCH_AHB_MST_USB 6
+
+/*! Misc registers. */
+#define APB_MISC_PP_STRAPPING_OPT_A 0x08
+#define APB_MISC_PP_PINMUX_GLOBAL 0x40
+#define APB_MISC_GP_HIDREV 0x804
+#define  GP_HIDREV_MAJOR_T210    0x1
+#define  GP_HIDREV_MAJOR_T210B01 0x2
+#define APB_MISC_GP_AUD_MCLK_CFGPADCTRL 0x8F4
+#define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34
+#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL 0xA98
+#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL 0xA9C
+#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL 0xAB4
+#define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL 0xABC
+#define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64
+#define APB_MISC_GP_WIFI_RST_CFGPADCTRL 0xB68
+
+/*! System registers. */
+#define AHB_ARBITRATION_XBAR_CTRL 0xE0
+#define AHB_AHB_SPARE_REG 0x110
+
+/*! Secure boot registers. */
+#define SB_CSR 0x0
+#define  SB_CSR_NS_RST_VEC_WR_DIS    (1 << 1)
+#define  SB_CSR_PIROM_DISABLE        (1 << 4)
+#define SB_AA64_RESET_LOW  0x30
+#define  SB_AA64_RST_AARCH64_MODE_EN (1 << 0)
+#define SB_AA64_RESET_HIGH 0x34
+
+/*! SOR registers. */
+#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB   0x1E8
+#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB 0x21C
+#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB   0x208
+#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB   0x20C
+
+/*! RTC registers. */
+#define APBDEV_RTC_SECONDS        0x8
+#define APBDEV_RTC_SHADOW_SECONDS 0xC
+#define APBDEV_RTC_MILLI_SECONDS  0x10
+
+/*! SYSCTR0 registers. */
+#define SYSCTR0_CNTFID0     0x20
+#define SYSCTR0_CNTCR       0x00
+#define SYSCTR0_COUNTERID0  0xFE0
+#define SYSCTR0_COUNTERID1  0xFE4
+#define SYSCTR0_COUNTERID2  0xFE8
+#define SYSCTR0_COUNTERID3  0xFEC
+#define SYSCTR0_COUNTERID4  0xFD0
+#define SYSCTR0_COUNTERID5  0xFD4
+#define SYSCTR0_COUNTERID6  0xFD8
+#define SYSCTR0_COUNTERID7  0xFDC
+#define SYSCTR0_COUNTERID8  0xFF0
+#define SYSCTR0_COUNTERID9  0xFF4
+#define SYSCTR0_COUNTERID10 0xFF8
+#define SYSCTR0_COUNTERID11 0xFFC
+
+/*! TMR registers. */
+#define TIMERUS_CNTR_1US          (0x10 + 0x0)
+#define TIMERUS_USEC_CFG          (0x10 + 0x4)
+#define TIMER_TMR8_TMR_PTV        0x78
+#define TIMER_TMR9_TMR_PTV        0x80
+#define  TIMER_EN          (1 << 31)
+#define  TIMER_PER_EN      (1 << 30)
+#define TIMER_TMR8_TMR_PCR        0x7C
+#define TIMER_TMR9_TMR_PCR        0x8C
+#define  TIMER_INTR_CLR    (1 << 30)
+
+#define TIMER_WDT4_CONFIG         (0x100 + 0x80)
+#define  TIMER_SRC(TMR) (TMR & 0xF)
+#define  TIMER_PER(PER) ((PER & 0xFF) << 4)
+#define  TIMER_SYSRESET_EN (1 << 14)
+#define  TIMER_PMCRESET_EN (1 << 15)
+#define TIMER_WDT4_COMMAND        (0x108 + 0x80)
+#define  TIMER_START_CNT   (1 << 0)
+#define  TIMER_CNT_DISABLE (1 << 1)
+#define TIMER_WDT4_UNLOCK_PATTERN (0x10C + 0x80)
+#define  TIMER_MAGIC_PTRN 0xC45A
+
+/*! I2S registers. */
+#define I2S1_CG   0x88
+#define I2S1_CTRL 0xA0
+#define I2S2_CG   0x188
+#define I2S2_CTRL 0x1A0
+#define I2S3_CG   0x288
+#define I2S3_CTRL 0x2A0
+#define I2S4_CG   0x388
+#define I2S4_CTRL 0x3A0
+#define I2S5_CG   0x488
+#define I2S5_CTRL 0x4A0
+#define  I2S_CG_SLCG_ENABLE (1 << 0)
+#define  I2S_CTRL_MASTER_EN (1 << 10)
+
+/*! PWM registers. */
+#define PWM_CONTROLLER_PWM_CSR_0 0x00
+#define PWM_CONTROLLER_PWM_CSR_1 0x10
+#define  PWM_CSR_EN (1 << 31)
+
+/*! Special registers. */
+#define EMC_SCRATCH0 0x324
+#define  EMC_HEKA_UPD (1 << 30)
+#define  EMC_SEPT_RUN (1 << 31)
+
+/*! Flow controller registers. */
+#define FLOW_CTLR_HALT_COP_EVENTS  0x4
+#define  HALT_COP_GIC_IRQ        (1 << 9)
+#define  HALT_COP_LIC_IRQ        (1 << 11)
+#define  HALT_COP_SEC            (1 << 23)
+#define  HALT_COP_MSEC           (1 << 24)
+#define  HALT_COP_USEC           (1 << 25)
+#define  HALT_COP_JTAG           (1 << 28)
+#define  HALT_COP_WAIT_EVENT     (1 << 30)
+#define  HALT_COP_STOP_UNTIL_IRQ (1 << 31)
+#define  HALT_COP_MAX_CNT        0xFF
+#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14
+#define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C
+#define FLOW_CTLR_HALT_CPU3_EVENTS 0x24
+#define FLOW_CTLR_CPU0_CSR 0x8
+#define FLOW_CTLR_CPU1_CSR 0x18
+#define FLOW_CTLR_CPU2_CSR 0x20
+#define FLOW_CTLR_CPU3_CSR 0x28
+#define FLOW_CTLR_RAM_REPAIR 0x40
+#define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98
+
+/*! USB controller registers. */
+#define USB1_UTMIP_BAT_CHRG_CFG0 0x830
+#define  BAT_CHRG_CFG0_OP_SRC_EN    (1 << 3)
+#define  BAT_CHRG_CFG0_PWRDOWN_CHRG (1 << 0)
+
+#endif

bdk/soc/uart.c

@@ -0,0 +1,169 @@
+/*
+* Copyright (c) 2018 naehrwert
+* Copyright (c) 2019-2020 CTCaer
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms and conditions of the GNU General Public License,
+* version 2, as published by the Free Software Foundation.
+*
+* This program is distributed in the hope it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include <soc/uart.h>
+#include <soc/clock.h>
+#include <soc/t210.h>
+#include <utils/util.h>
+
+/* UART A, B, C, D and E. */
+static const u32 uart_baseoff[5] = { 0, 0x40, 0x200, 0x300, 0x400 };
+
+void uart_init(u32 idx, u32 baud)
+{
+	uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
+
+	// Make sure no data is being sent.
+	uart_wait_idle(idx, UART_TX_IDLE);
+
+	// Set clock.
+	bool clk_type = clock_uart_use_src_div(idx, baud);
+
+	// Misc settings.
+	u32 div = clk_type ? ((8 * baud + 408000000) / (16 * baud)) : 1; // DIV_ROUND_CLOSEST.
+	uart->UART_IER_DLAB = 0; // Disable interrupts.
+	uart->UART_LCR = UART_LCR_DLAB | UART_LCR_WORD_LENGTH_8; // Enable DLAB & set 8n1 mode.
+	uart->UART_THR_DLAB = (u8)div; // Divisor latch LSB.
+	uart->UART_IER_DLAB = (u8)(div >> 8); // Divisor latch MSB.
+	uart->UART_LCR = UART_LCR_WORD_LENGTH_8; // Disable DLAB.
+	(void)uart->UART_SPR;
+
+	// Setup and flush fifo.
+	uart->UART_IIR_FCR = UART_IIR_FCR_EN_FIFO;
+	(void)uart->UART_SPR;
+	usleep(20);
+	uart->UART_MCR = 0; // Disable hardware flow control.
+	usleep(96);
+	uart->UART_IIR_FCR = UART_IIR_FCR_EN_FIFO | UART_IIR_FCR_TX_CLR | UART_IIR_FCR_RX_CLR;
+
+	// Wait 3 symbols for baudrate change.
+	usleep(3 * ((baud + 999999) / baud));
+	uart_wait_idle(idx, UART_TX_IDLE | UART_RX_IDLE);
+}
+
+void uart_wait_idle(u32 idx, u32 which)
+{
+	uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
+	if (UART_TX_IDLE & which)
+	{
+		while (!(uart->UART_LSR & UART_LSR_TMTY))
+			;
+	}
+	if (UART_RX_IDLE & which)
+	{
+		while (uart->UART_LSR & UART_LSR_RDR)
+			;
+	}
+}
+
+void uart_send(u32 idx, const u8 *buf, u32 len)
+{
+	uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
+
+	for (u32 i = 0; i != len; i++)
+	{
+		while (!(uart->UART_LSR & UART_LSR_THRE))
+			;
+		uart->UART_THR_DLAB = buf[i];
+	}
+}
+
+u32 uart_recv(u32 idx, u8 *buf, u32 len)
+{
+	uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
+	u32 timeout = get_tmr_us() + 250;
+	u32 i;
+
+	for (i = 0; ; i++)
+	{
+		while (!(uart->UART_LSR & UART_LSR_RDR))
+		{
+			if (timeout < get_tmr_us())
+				break;
+			if (len && len < i)
+				break;
+		}
+		if (timeout < get_tmr_us())
+			break;
+
+		buf[i] = uart->UART_THR_DLAB;
+		timeout = get_tmr_us() + 250;
+	}
+
+	return i ? (len ? (i - 1) : i) : 0;
+}
+
+void uart_invert(u32 idx, bool enable, u32 invert_mask)
+{
+	uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
+
+	if (enable)
+		uart->UART_IRDA_CSR |= invert_mask;
+	else
+		uart->UART_IRDA_CSR &= ~invert_mask;
+	(void)uart->UART_SPR;
+}
+
+u32 uart_get_IIR(u32 idx)
+{
+	uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
+
+	return uart->UART_IIR_FCR;
+}
+
+void uart_set_IIR(u32 idx)
+{
+	uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
+
+	uart->UART_IER_DLAB &= ~UART_IER_DLAB_IE_EORD;
+	(void)uart->UART_SPR;
+	uart->UART_IER_DLAB |= UART_IER_DLAB_IE_EORD;
+	(void)uart->UART_SPR;
+}
+
+void uart_empty_fifo(u32 idx, u32 which)
+{
+	uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]);
+
+	uart->UART_MCR = 0;
+	(void)uart->UART_SPR;
+	usleep(96);
+
+	uart->UART_IIR_FCR = UART_IIR_FCR_EN_FIFO | UART_IIR_FCR_TX_CLR | UART_IIR_FCR_RX_CLR;
+	(void)uart->UART_SPR;
+	usleep(18);
+	u32 tries = 0;
+
+	if (UART_IIR_FCR_TX_CLR & which)
+	{
+		while (tries < 10 && uart->UART_LSR & UART_LSR_TMTY)
+		{
+			tries++;
+			usleep(100);
+		}
+		tries = 0;
+	}
+
+	if (UART_IIR_FCR_RX_CLR & which)
+	{
+		while (tries < 10 && !uart->UART_LSR & UART_LSR_RDR)
+		{
+			tries++;
+			usleep(100);
+		}
+	}
+}

bdk/soc/uart.h

@@ -0,0 +1,87 @@
+/*
+* Copyright (c) 2018 naehrwert
+* Copyright (c) 2019-2020 CTCaer
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms and conditions of the GNU General Public License,
+* version 2, as published by the Free Software Foundation.
+*
+* This program is distributed in the hope it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+* more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef _UART_H_
+#define _UART_H_
+
+#include <utils/types.h>
+
+#define UART_A 0
+#define UART_B 1
+#define UART_C 2
+#define UART_D 3
+#define UART_E 4
+
+#define BAUD_115200 115200
+
+#define UART_TX_IDLE 0x1
+#define UART_RX_IDLE 0x2
+
+#define UART_TX_FIFO_FULL 0x100
+#define UART_RX_FIFO_EMPTY 0x200
+
+#define UART_INVERT_RXD 0x01
+#define UART_INVERT_TXD 0x02
+#define UART_INVERT_CTS 0x04
+#define UART_INVERT_RTS 0x08
+
+#define UART_IER_DLAB_IE_EORD 0x20
+
+#define UART_LCR_DLAB 0x80
+#define UART_LCR_STOP 0x4
+#define UART_LCR_WORD_LENGTH_8 0x3
+
+#define UART_LSR_RDR 0x1
+#define UART_LSR_THRE 0x20
+#define UART_LSR_TMTY 0x40
+#define UART_LSR_FIFOE 0x80
+
+#define UART_IIR_FCR_TX_CLR 0x4
+#define UART_IIR_FCR_RX_CLR 0x2
+#define UART_IIR_FCR_EN_FIFO 0x1
+
+#define UART_MCR_RTS 0x2
+#define UART_MCR_DTR 0x1
+
+typedef struct _uart_t
+{
+	/* 0x00 */ vu32 UART_THR_DLAB;
+	/* 0x04 */ vu32 UART_IER_DLAB;
+	/* 0x08 */ vu32 UART_IIR_FCR;
+	/* 0x0C */ vu32 UART_LCR;
+	/* 0x10 */ vu32 UART_MCR;
+	/* 0x14 */ vu32 UART_LSR;
+	/* 0x18 */ vu32 UART_MSR;
+	/* 0x1C */ vu32 UART_SPR;
+	/* 0x20 */ vu32 UART_IRDA_CSR;
+	/* 0x24 */ vu32 UART_RX_FIFO_CFG;
+	/* 0x28 */ vu32 UART_MIE;
+	/* 0x2C */ vu32 UART_VENDOR_STATUS;
+	/* 0x30 */ u8 _pad_30[0xC];
+	/* 0x3C */ vu32 UART_ASR;
+} uart_t;
+
+void uart_init(u32 idx, u32 baud);
+void uart_wait_idle(u32 idx, u32 which);
+void uart_send(u32 idx, const u8 *buf, u32 len);
+u32  uart_recv(u32 idx, u8 *buf, u32 len);
+void uart_invert(u32 idx, bool enable, u32 invert_mask);
+u32  uart_get_IIR(u32 idx);
+void uart_set_IIR(u32 idx);
+void uart_empty_fifo(u32 idx, u32 which);
+
+#endif